Display device with combined driving methods

Patent metadata

Field	Value
Publication number	US-12361871-B2
Application number	US-202318512214-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Dec 20, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A display device with combined pixel driving methods includes a pixel unit in which a plurality of pixels are arranged, each pixel including a luminous element and a pixel circuit connected to the luminous element, and a driver configured to generate and supply a driving current, a clock signal, and a driving method selection signal to the pixel unit, wherein the pixel circuit of each of the plurality of pixels drives light emission of the luminous element based on the driving method selection signal through one of a pulse width modulation (PWM) driving method or a pulse amplitude modulation (PAM) driving method.

First claim

What is claimed is:

1. A display device comprising:
a plurality of pixels, wherein each of the plurality of pixels includes a luminous element and a pixel circuit connected to the luminous element; and
a processor configured to generate and supply a driving current, a clock signal, and a driving method selection signal to the plurality of pixels,
wherein the pixel circuit of each of the plurality of pixels includes a pulse width modulation (PWM) driving circuit and a pulse amplitude modulation (PAM) driving circuit and drives light emission of the luminous element by an operation of the PWM driving circuit or the PAM driving circuit based on the driving method selection signal,
wherein the processor is further configured to generate the driving method selection signal to select one of the PAM driving circuit to operate when a gradation extracted based on image data is included in a high-gradation region or the PWM driving circuit to operate when the gradation extracted based on the image data is included in a low-gradation region,
wherein a predetermined number of digits starting from the most significant bit of the image data are set as region representation bits that are configured to select either one of the PAM driving circuit or the PWM driving circuit to drive the luminous element based on the image data, and gradation representation bits are set to follow the region representation bits and are used to express graduation based on the image data for each pixel,
wherein the processor is further configured to convert the image data with a size of n bits into the region representation bits with a size of 2 bits and the gradation representation bits with a size of n/2 bits.

2. The display device of claim 1 , wherein
the region representation bits are determined to represent which region of a first region, a second region, a third region, and a fourth region the image data belongs to, and
the first region, the second region, the third region, and the fourth region are formed by dividing an entire gradation region including 2 n gradations represented by n bits.

3. The display device of claim 2 , wherein
when the region representation bits are “00,” the image data belongs to the first region,
when the region representation bits are “01,” the image data belongs to the second region,
when the region representation bits are “10,” the image data belongs to the third region, and
when the region representation bits are “11,” the image data belongs to the fourth region.

4. The display device of claim 3 , wherein
the driving method selection signal is generated such that the pixel circuit drives light emission of the luminous element by an operation of the PWM driving circuit when the region representation bits are one of “00,” “01,” or “10,” and
the driving method selection signal is generated such that the pixel circuit drives light emission of the luminous element by an operation of the PAM driving circuit when the region representation bits are “11”.

5. The display device of claim 2 , wherein the first region, the second region, the third region, and the fourth region are formed by dividing the entire gradation region from low gradation to high gradation into ratios of 1/8, 1/8, 1/4, and 1/2, which are respectively assigned thereto.

Assignees

• Sapien Semiconductors Inc

Inventors

• Jung Jun Young
• Lee Myunghee

Classifications

• G09G3/2011

  by amplitude modulation · CPC title

• G09G3/2014 Primary

  by modulation of the duration of a single pulse during which the logic level remains constant · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title

• G09G2320/0271

  Adjustment of the gradation levels within the range of the gradation scale, e.g. by redistribution or clipping · CPC title