System and method for flushing data using mapping page ownership

Patent metadata

Field	Value
Publication number	US-12360917-B2
Application number	US-202318488213-A
Country	US
Kind code	B2
Filing date	Oct 17, 2023
Priority date	Oct 17, 2023
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

A method, computer program product, and computing system for generating a plurality of page buffers from a log memory system of the storage system using a persistent memory organization policy. A plurality of physical layer blocks (PLBs) are generated from the log memory system using the persistent memory organization policy. A set of page buffers are allocated from the plurality of page buffers to a first mapping page of a plurality of mapping pages. A PLB is allocated from the plurality of PLBs to a second mapping page of the plurality of mapping pages. One or more IO requests are processed using one or more of the first mapping page and the second mapping page.

First claim

What is claimed is:

1. A computer-implemented method, executed on a computing device, comprising:
generating a plurality of page buffers from a log memory system of the storage system using a persistent memory organization policy;
generating a plurality of physical layer blocks (PLBs) from the log memory system using the persistent memory organization policy;
allocating a set of page buffers from the plurality of page buffers to a first mapping page of a plurality of mapping pages;
allocating a PLB from the plurality of PLBs to a second mapping page of the plurality of mapping pages; and
processing one or more IO requests using one or more of the first mapping page and the second mapping page.

2. The computer-implemented method of claim 1 , wherein the plurality of page buffers are located in non-volatile random-access memory (NVRAM) persistent storage within the log memory system.

3. The computer-implemented method of claim 2 , wherein the plurality of PLBs are located in solid state drive (SSD) persistent storage within the log memory system.

4. The computer-implemented method of claim 3 , wherein processing the one or more IO requests using the first mapping page includes flushing data from the first mapping page by flushing the set of page buffers to the storage system.

5. The computer implemented method of claim 4 , wherein processing the one or more IO requests using the second mapping page includes flushing data from the second mapping page by flushing the PLB to the storage system.

6. The computer implemented method of claim 4 , further comprising:
monitoring a ratio of the plurality of page buffers to the plurality of PLBs within the log memory system.

7. The computer implemented method of claim 6 , further comprising:
iteratively adjusting the persistent memory organization policy based upon, at least in part, the ratio of the plurality of page buffers to the plurality of PLBs within the log memory system.

8. A computer program product residing on a non-transitory computer readable medium having a plurality of instructions stored thereon which, when executed by a processor, cause the processor to perform operations comprising:
generating a plurality of page buffers from a log memory system of the storage system using a persistent memory organization policy;
generating a plurality of physical layer blocks (PLBs) from the log memory system using the persistent memory organization policy;
allocating a set of page buffers from the plurality of page buffers to a first mapping page of a plurality of mapping pages;
allocating a PLB from the plurality of PLBs to a second mapping page of the plurality of mapping pages; and
processing one or more IO requests using one or more of the first mapping page and the second mapping page.

9. The computer program product of claim 8 , wherein the plurality of page buffers are located in non-volatile random-access memory (NVRAM) persistent storage within the log memory system.

10. The computer program product of claim 9 , wherein the plurality of PLBs are located in solid state drive (SSD) persistent storage within the log memory system.

11. The computer program product of claim 10 , wherein processing the one or more IO requests using the first mapping page includes flushing data from the first mapping page by flushing the set of page buffers to the storage system.

12. The computer program product of claim 11 , wherein processing the one or more IO requests using the second mapping page includes flushing data from the second mapping page by flushing the PLB to the storage system.

13. The computer program product of claim 11 , wherein the operations further comprise:
monitoring a ratio of the plurality of page buffers to the plurality of PLBs within the log memory system.

14. The computer program product of claim 13 , wherein the operations further comprise:
iteratively adjusting the persistent memory organization policy based upon, at least in part, the ratio of the plurality of page buffers to the plurality of PLBs within the log memory system.

15. A computing system comprising:
a memory; and
a processor configured to generate a plurality of page buffers from a log memory system of the storage system using a persistent memory organization policy, to generate a plurality of physical layer blocks (PLBs) from the log memory system using the persistent memory organization policy, to allocate a set of page buffers from the plurality of page buffers to a first mapping page of a plurality of mapping pages, to allocate a PLB from the plurality of PLBs to a second mapping page of the plurality of mapping pages, and to process one or more IO requests using one or more of the first mapping page and the second mapping page.

16. The computing system of claim 15 , wherein the plurality of page buffers are located in non-volatile random-access memory (NVRAM) persistent storage within the log memory system.

17. The computing system of claim 16 , wherein the plurality of PLBs are located in solid state drive (SSD) persistent storage within the log memory system.

18. The computing system of claim 17 , wherein processing the one or more IO requests using the first mapping page includes flushing data from the first mapping page by flushing the set of page buffers to the storage system.

19. The computing system of claim 18 , wherein processing the one or more IO requests using the second mapping page includes flushing data from the second mapping page by flushing the PLB to the storage system.

20. The computing system of claim 18 , wherein the processor is further configured to:
monitor a ratio of the plurality of page buffers to the plurality of PLBs within the log memory system; and
iteratively adjust the persistent memory organization policy based upon, at least in part, the ratio of the plurality of page buffers to the plurality of PLBs within the log memory system.

Assignees

• Dell Products Lp

Inventors

• Baruch Oran
• Vankamamidi Vamsi
• Rahamim Maor

Classifications

• G06F2212/152

  Virtualized environment, e.g. logically partitioned system · CPC title

• G06F2212/1032

  Reliability improvement, data loss prevention, degraded operation etc · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title