Performance benchmark for host performance booster

Patent metadata

Field	Value
Publication number	US-12360872-B2
Application number	US-202117597985-A
Country	US
Kind code	B2
Filing date	Mar 16, 2021
Priority date	Mar 16, 2021
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Methods, systems, and devices for performance benchmark for host performance booster are described. The memory system may receive a plurality of read commands from a host system. The memory system may detect a pattern of random physical addresses as part of the plurality of read commands and increase an amount of space in a cache of the memory system based on the detected pattern. In some cases, the amount of space may be used for mapping between logical block addresses and physical addresses. The memory system may determine, for a different plurality of read commands, whether a rate of cache hits for a portion of the mapping satisfies a threshold. In some cases, the memory system may determine whether to activate a host performance booster mode based on determining whether the rate of cache hits satisfies the threshold.

First claim

What is claimed is:

1. A memory system, comprising:
one or more memory arrays comprising non-volatile memory cells;
a cache memory comprising volatile memory cells; and
processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
receive, from a host system, a first plurality of read commands;
detect a pattern of random physical addresses accessed as part of the first plurality of read commands;
increase, in the cache memory based at least in part on detecting the pattern, an amount of space for mapping logical block addresses to physical addresses, wherein increasing the amount of space in the cache memory comprises increasing an active cache space of the cache memory to include an extended cache portion;
receive, from the host system, a second plurality of read commands indicating to read data from a first region of the non-volatile memory cells;
store, in the extended cache portion of the cache memory based at least in part on reading the data from the first region of the non-volatile memory cells, a first portion of a mapping between a set of logical block addresses and a set of physical addresses associated with the first region of the non-volatile memory cells;
determine, for the second plurality of read commands based at least in part on storing the first portion of the mapping in the extended cache portion of the cache memory, that a first rate of cache hits of the extended cache portion fails to satisfy a threshold associated with activation of a host performance booster mode;
refrain from activating the host performance booster mode for the first region of the non-volatile memory cells based at least in part on the first rate of cache hits of the extended cache portion failing to satisfy the threshold associated with activation of the host performance booster mode;
receive, from the host system, a third plurality of read commands indicating to read second data from the first region of the non-volatile memory cells;
adjust the threshold associated with activation of the host performance booster mode based at least in part on the first rate of cache hits and a parse rate of the memory system;
determine, for the third plurality of read commands, that a second rate of cache hits of the extended cache portion satisfies the adjusted threshold associated with activation of the host performance booster mode;
activate the host performance booster mode for the first region of the non-volatile memory cells based at least in part on increasing the amount of space in the cache memory and determining that the second rate of cache hits of the extended cache portion satisfies the adjusted threshold, wherein the host performance booster mode is deactivated for a second region of the non-volatile memory cells; and
transmit, to the host system, a second portion of the mapping between the set of logical block addresses and the set of physical addresses associated with the first region of the non-volatile memory cells based at least in part on activating the host performance booster mode and the second rate of cache hits for the first portion of the mapping satisfying the threshold.

2. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
determine that the second rate of cache hits for the first portion of the mapping is below the threshold, wherein activating the host performance booster mode is based at least in part on the determining that the second rate of cache hits for the first portion of the mapping is below the threshold.

3. The memory system of claim 2 , wherein the processing circuitry is further configured to cause the memory system to:
receive, from the host system, a read command based at least in part on activating the host performance booster mode; and
perform, using the host performance booster mode, a read operation associated with the read command based at least in part on receiving the read command and activating the host performance booster mode.

4. The memory system of claim 1 , wherein the processing circuitry is further configured to cause the memory system to:
transmit, to the host system, an indication of an operating mode based at least in part on activating the host performance booster mode.

5. The memory system of claim 1 , wherein the host performance booster mode causes a second cache memory associated with the host system to store at least a portion of the mapping.

6. The memory system of claim 1 , wherein the first rate of cache hits is a frequency with which the memory system comprises a corresponding address in the cache memory for one or more incoming read commands.

7. A non-transitory computer-readable medium storing code comprising instructions, which when executed by one or more processors of an electronic device, cause the electronic device to:
receive, from a host system, a first plurality of read commands;
detect a pattern of random physical addresses accessed as part of the first plurality of read commands;
increase, in a cache memory of a memory system based at least in part on detecting the pattern, an amount of space for mapping logical block addresses to physical addresses, wherein increasing the amount of space in the cache memory comprises increasing an active cache space of the cache memory to include an extended cache portion;
receive, from the host system, a second plurality of read commands indicating to read data from a first region of non-volatile memory cells of the memory system;
store, in the extended cache portion of the cache memory based at least in part on reading the data from the first region of the non-volatile memory cells, a first portion of a mapping between a set of logical block addresses and a set of physical addresses associated with the first region of the non-volatile memory cells;
determine, for the second plurality of read commands based at least in part on storing the first portion of the mapping in the extended cache portion of the cache memory, that a first rate of cache hits of the extended cache portion fails to satisfy a threshold associated with activation of a host performance booster mode;
refrain from activating the host performance booster mode for the first region of the non-volatile memory cells based at least in part on the first rate of cache hits of the extended cache portion failing to satisfy the threshold associated with activation of the host performance booster mode;
receive, from the host system, a third plurality of read commands indicating to read second data from the first region of the non-volatile memory cells;
adjust the threshold associated with activation of the host performance booster mode based at least in part on the first rate of cache hits and a parse rate of the memory system;
determine, for the third plurality of read commands, that a second rate of cache hits of the extended cache portion satisfies the adjusted threshold associated with activation of the host performance booster mode;
activate the host performance booster mode for the first region of the non-volatile memory cells based at least in part on increasing the amount of space in the cache memory and determining that the second rate of cache hits of the extended cache portion satisfies the adjusted threshold, wherein the host performance booster mode is deactivated for a second region of the non-volatile memory cells; and
transmit, to the host system, a second portion of the mapping between the set of logical block addresses and the set of physical addresses associated with the first region of the non-volatile memory cells based at least in part on activating the host performance booster mode and the second rate of cache hits for the first portion of the mapping satisfying t

Assignees

• Micron Technology Inc

Inventors

• Zhao Bin
• Wang Lingyun

Classifications

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title

• G06F12/0877

  Cache access modes · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F11/3409 Primary

  for performance assessment · CPC title