CXL protocol enablement for test environment systems and methods

Patent metadata

Field	Value
Publication number	US-12360868-B2
Application number	US-202318129394-A
Country	US
Kind code	B2
Filing date	Mar 31, 2023
Priority date	Sep 21, 2022
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

Efficient and effective testing systems and methods are presented. In one embodiment, a testing system includes: a user interface configured to enable user interaction with the system; a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the DUTs are compute express link (CXL) protocol compliant; and a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing. In one exemplary implementation, the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

First claim

The invention claimed is:

1. A testing system comprising:
a user interface configured to enable user interaction with the testing system;
a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the plurality of DUTs are compute express link (CXL) protocol compliant; and
a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing, and wherein the plurality of DUTs are included in a system memory range.

2. A testing system of claim 1 , wherein the tester prevents testing of a first one of the plurality of DUTs from detrimentally interfering with testing of a second one of the plurality of DUTs.

3. A testing system of claim 1 , wherein the plurality of DUTs are memory devices and the tester is configured to prevent detrimental access to the plurality of DUTs by different entities.

4. A testing system of claim 1 , wherein the plurality of DUTs are included in separate memory ranges.

5. A testing system of claim 1 , wherein the plurality of DUTs are memory devices.

6. A testing system of claim 1 , wherein the plurality of DUTs operate as extended memory.

7. A testing system of claim 1 , wherein user configuration requirements are mapped to characteristics of the plurality of DUTs.

8. A testing system of claim 1 , wherein the tester comprises a host central processing unit configured to direct operations of the direct testing of the plurality of DUTs.

9. A testing system of claim 1 , wherein a host central processing unit is configured to track and coordinate central processing unit (CPU) cache accesses with user requirements.

10. A testing method comprising:
directing testing of devices under test (DUTs), wherein the testing comprises compute express link (CXL) protocol communication with the DUTs; and
preventing testing operations of the DUTs from detrimentally interfering with one another, and wherein the preventing testing operations of the DUTs from detrimentally interfering with one another comprises assigning separate memory ranges to the DUTs.

11. A testing method of claim 10 further comprising determining if a particular one of the DUTs is a CXL compliant device.

12. A testing method of claim 10 wherein determining if a particular one of the DUTs is a CXL compliant device is performed as part of an enumeration process.

13. A testing method of claim 12 wherein basic input/output system (BIOS) operations determine if the particular one of the DUTs is a CXL compliant device.

14. A testing method of claim 10 further comprising determining characteristics of the DUTs.

15. A testing method of claim 10 further comprising mapping user configuration requirements to characteristics of the DUTs.

16. A testing method of claim 10 further comprising tracing and coordinating central processing unit (CPU) cache accesses with user requirements.

17. A testing method of claim 10 further comprising using CXL protocol features on the DUTs under testing conditions.

18. A testing system comprising:
a user interface configured to enable user interaction with the testing system;
a test board configured to communicatively couple with a plurality of devices under test (DUTs), wherein the plurality of DUTs are compute express link (CXL) protocol compliant; and
a tester configured to direct testing of the plurality of DUTs, wherein the tester manages testing of the plurality of DUTs, including managing CXL protocol aspects of the testing, and wherein the plurality of DUTs are automatically mapped to separate system memory ranges.

19. A testing system of claim 18 , wherein the tester prevents detrimental interference with testing of one of the plurality of DUTs.

20. A testing system of claim 18 , wherein the tester is configured to prevent detrimental access to the plurality of DUTs by one another.

Assignees

• Advantest Corp

Inventors

• Malisic Srdjan
• Yuan Chi
• Chen Jenny

Classifications

• G06F2221/034

  Test or assess a computer or a system · CPC title

• G06F21/53 Primary

  by executing in a restricted environment, e.g. sandbox or secure virtual machine · CPC title

• G06F11/2733

  Test interface between tester and unit under test · CPC title

• G06F11/27

  Built-in tests · CPC title

• G06F11/2205

  using arrangements specific to the hardware being tested · CPC title