Coalescing adjacent gather/scatter operations

Patent metadata

Field	Value
Publication number	US-12360774-B2
Application number	US-202218092298-A
Country	US
Kind code	B2
Filing date	Dec 31, 2022
Priority date	Dec 26, 2012
Publication date	Jul 15, 2025
Grant date	Jul 15, 2025

Abstract

According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

First claim

What is claimed is:

1. A processor comprising:
a data cache to cache data;
an instruction cache to cache instructions;
a decode unit coupled to the instruction cache, the decode unit to decode the instructions, including a first instruction, the first instruction having a first field to specify a first source vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits; and
an execution unit coupled to the decode unit, coupled to the first source vector register, and coupled to the 64-bit general-purpose register, the execution unit to perform operations corresponding to the first instruction, including to:
for mask bits of the mask that are one:
store a corresponding structure to a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element from a 64-bit data element position of the first source vector register corresponding to the mask bit, a second 64-bit data element from a 64-bit data element position of a second source vector register corresponding to the mask bit, and a third 64-bit data element from a 64-bit data element position of a third source vector register corresponding to the mask bit; and

for mask bits of the mask that are zero, not store a corresponding structure to the memory.

2. The processor of claim 1 , wherein the mask register is a 16-bit register, and wherein the first source vector register is a 128-bit vector register.

3. The processor of claim 1 , wherein the first instruction has a data element width field to indicate the data element width of 64-bits.

4. The processor of claim 1 , wherein the first, second, and third source vector registers are a sequence of registers.

5. The processor of claim 1 , further comprising a plurality of mask registers including the mask register.

6. The processor of claim 5 , wherein the third field is a three-bit field.

7. The processor of claim 1 , wherein the mask register is one of a set of registers, the set of registers including a plurality of mask registers and a given register, the processor not supporting use of the given register for masking.

8. The processor of claim 1 , wherein not all bits of the mask register are utilized by the first instruction.

9. The processor of claim 1 , wherein the processor has a reduced instruction set computing (RISC) architecture.

10. A system on a chip (SoC) comprising:
a memory controller unit; and
a processor core coupled with the memory controller unit, the processor core comprising:
a data cache to cache data;
an instruction cache to cache instructions;
a decode unit coupled to the instruction cache, the decode unit to decode the instructions, including a first instruction, the first instruction having a first field to specify a first source vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits; and
an execution unit coupled to the decode unit, coupled to the first source vector register, and coupled to the 64-bit general-purpose register, the execution unit to perform operations corresponding to the first instruction, including to:
for mask bits of the mask that are one:
store a corresponding structure to a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element from a 64-bit data element position of the first source vector register corresponding to the mask bit, a second 64-bit data element from a 64-bit data element position of a second source vector register corresponding to the mask bit, and a third 64-bit data element from a 64-bit data element position of a third source vector register corresponding to the mask bit; and

for mask bits of the mask that are zero, not store a corresponding structure to the memory.

11. The SoC of claim 10 , further comprising a display logic to couple to one or more displays coupled with the processor core, wherein the mask register is a 16-bit register, and wherein the first source vector register is a 128-bit vector register, and wherein the first instruction has a data element width field to indicate the data element width of 64-bits.

12. The SoC of claim 10 , further comprising an image processor coupled with the processor core, wherein the processor core further comprises a plurality of mask registers including the mask register, and wherein the first, second, and third source vector registers are a sequence of registers.

13. The SoC of claim 10 , further comprising a graphics processing unit (GPU) coupled with the processor core, wherein the mask register is one of a set of registers, the set of registers including a plurality of mask registers and a given register, the processor core not supporting use of the given register for masking.

14. The SoC of claim 10 , further comprising a Peripheral Component Interconnect (PCI) Express bus interface coupled to the processor core, wherein not all bits of the mask register are utilized by the first instruction, wherein the mask register is a 16-bit register, and wherein the first source vector register is a 128-bit vector register, and wherein the first instruction has a data element width field to indicate the data element width of 64-bits.

15. A system comprising:
a system memory; and
a processor coupled with the system memory, the processor comprising:
a data cache to cache data;
an instruction cache to cache instructions;
a decode unit coupled to the instruction cache, the decode unit to decode the instructions, including a first instruction, the first instruction having a first field to specify a first source vector register, the first instruction having a second field to specify a 64-bit general-purpose register as a source of a base address, the first instruction having a third field to specify a mask register as a source of a mask, and the first instruction to indicate a data element width of 64-bits; and
an execution unit coupled to the decode unit, coupled to the first source vector register, and coupled to the 64-bit general-purpose register, the execution unit to perform operations corresponding to the first instruction, including to:
for mask bits of the mask that are one:
store a corresponding structure to a memory based on the base address, the structure to include, as contiguous elements in the memory, a first 64-bit data element from a 64-bit data element position of the first source vector register corresponding to the mask bit, a second 64-bit data element from a 64-bit data element position of a second source vector register corresponding to the mask bit, and a third 64-bit data element from a 64-bit data element position of a third source vector register corresponding to the mask bit; and

for mask bits of the mask that are zero, not store a corresponding structure to the memory.

16. The system of claim 15 , further comprising a communication device coupled to the processor, wherein the processor further comprises a plurality of mask registers including the mask register, and wherein the first, second, and third source vector registers are a sequence of registers.

17. The system of claim 15 , further comprising a Peripheral Componen

Assignees

• Intel Corp

Inventors

• Forsyth Andrew T
• Hickmann Brian J
• Hall Jonathan C
• Hughes Christopher J

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3804

  for branches, e.g. hedging, branch folding · CPC title

• G06F9/30098

  Register arrangements · CPC title

• G06F2212/1016

  Performance improvement · CPC title