Display panel and display apparatus

Patent metadata

Field	Value
Publication number	US-12356818-B2
Application number	US-202418661658-A
Country	US
Kind code	B2
Filing date	May 12, 2024
Priority date	Oct 14, 2019
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A display substrate including a display area, where the display area includes multiple pixel units in an array, in at least two adjacent rows of pixel units, a connection point between first and second power lines is in the first pixel unit, but is not in the second pixel unit; in at least two adjacent columns of pixel units, respective connection points between the first power lines and the second power lines are not on a straight line; and the display area includes at least two display sub-areas along an extending direction of the second power line; for any two display sub-areas, a number of the first pixel units in one of the two display sub-areas closer to a first power bus is less than a number of the first pixel units in the other of the two display sub-areas farther away from the first power bus.

First claim

What is claimed is:

1. A display substrate, comprising a display area, wherein the display area comprises a plurality of pixel units arranged in an array, each of the plurality of pixel units comprises a driving transistor, each of at least part of rows of pixel units is correspondingly provided with a first power line, and each of at least part of columns of pixel units is correspondingly provided with a second power line; a first power bus is provided on one side of the display area in an extending direction of the second power line, and one end of the second power line is coupled to the first power bus; the plurality of pixel units are divided into a first pixel unit and a second pixel unit;
in at least two adjacent rows of pixel units, a connection point between the first power line and the second power line is in the first pixel unit, but is not in the second pixel unit;
in at least two adjacent columns of pixel units, respective connection points between the first power lines and the second power lines are not on a same straight line; and
the display area comprises at least two display sub-areas, and the at least two display sub-areas are disposed along the extending direction of the second power line; and for any two display sub-areas, a number of the first pixel units in one of the two display sub-areas closer to the first power bus is less than a number of the first pixel units in the other of the two display sub-areas farther away from the first power bus.

2. The display substrate of claim 1 , wherein in at least one second pixel unit, an active layer of the driving transistor is connected, through a first power line, to the second power line corresponding to the column of the second pixel unit.

3. The display substrate of claim 1 , wherein in the first pixel unit, an active layer of the driving transistor is electrically coupled to the second power line corresponding to the column in which the first pixel unit is located.

4. The display substrate of claim 1 , wherein in the second pixel unit, an active layer of the driving transistor is electrically coupled, through the first power line corresponding to the row in which the second pixel unit is located, to the second power line corresponding to the column in which any one first pixel unit in the same row as the second pixel unit is located.

5. The display substrate of claim 1 , wherein the display area comprises a plurality of display sub-areas arranged in an array, and each of the plurality of display sub-areas comprises at least one first pixel unit.

6. The display substrate of claim 5 , wherein each of the plurality of display sub-areas comprises a plurality of first pixel units, and the plurality of first pixel units located in a same display sub-area are located in a same column.

7. The display substrate of claim 6 , wherein the first pixel units in different display sub-areas are located in different columns.

8. The display substrate of claim 1 , wherein a second power bus is further provided on the other side of the display area in the extending direction of the second power line, the second power bus is coupled to the first power bus, and the other end of the second power line is coupled to the second power bus.

9. The display substrate of claim 1 , wherein a third power bus is provided on one side of the display area in an extending direction of the first power line, and one end of the first power bus is coupled to one end of the third power bus; and one end of the first power line is coupled to the third power bus.

10. The display substrate of claim 9 , wherein a fourth power bus is provided on the other side of the display area in the extending direction of the first power line, and the other end of the first power bus is coupled to one end of the fourth power bus; and the other end of the first power line is coupled to the fourth power bus.

11. The display substrate of claim 1 , wherein the pixel unit further comprises a storage capacitor, the storage capacitor comprises a first electrode plate and a second electrode plate opposite to each other, the first electrode plate is a gate layer of the driving transistor, the second power line is in the same layer as a source layer and a drain layer of the driving transistor, and the first power line is in the same layer as the second electrode plate.

12. An AMOLED display device, comprising the display substrate of claim 1 .

13. A display substrate, comprising a display area, wherein the display area comprises a plurality of pixel units arranged in an array, each of the plurality of pixel units comprises a driving transistor, each of at least part of rows of pixel units is correspondingly provided with a first power line, each of at least part of columns of pixel units is correspondingly provided with a second power line; a first power bus is provided on one side of the display area in an extending direction of the second power line, and one end of the second power line is coupled to the first power bus;
wherein the plurality of pixel units are divided into a first pixel unit and a second pixel unit;
each row of pixel units comprises at least one first pixel unit; an active layer of the driving transistor in the first pixel unit is electrically and directly coupled to the second power line corresponding to a column in which the first pixel unit is located, but is not directly coupled to the first power line corresponding to a row in which the first pixel unit is located; and
for at least one column of pixel units, each column of the at least one column comprises at least one second pixel unit; the driving transistor in the second pixel unit is electrically coupled, through the first power line corresponding to a row in which the second pixel unit is located, to the second power line corresponding to a column in which any one first pixel unit in the same row as the second pixel unit is located; the driving transistor in the second pixel unit is electrically and directly coupled to the first power line corresponding to the row in which the second pixel unit is located, but is not directly coupled to the second power line corresponding to the column in which any one first pixel unit in the same row as the second pixel unit is located,
wherein the display area comprises at least two display sub-areas, and the at least two display sub-areas are disposed along the extending direction of the second power line; and for any two display sub-areas, a number of the first pixel units in one of the two display sub-areas closer to the first power bus is less than a number of the first pixel units in the other of the two display sub-areas farther away from the first power bus.

14. An AMOLED display device, comprising the display substrate of claim 13 .

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Li Shaoru
• Wang Rui
• Yang Ni
• Wu Hailong

Classifications

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title