Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12356809-B2
Application number	US-202017263576-A
Country	US
Kind code	B2
Filing date	Apr 14, 2020
Priority date	Apr 14, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A display substrate includes: a base substrate including a display region and a non-display region surrounding the display region; a plurality of sub-pixels in the display region; a plurality of power lines in the display region, the plurality of power lines extending along a first direction, and being electrically connected to the plurality of sub-pixels and being configured to provide power signals for the plurality of sub-pixels; a plurality of dummy sub-pixels in the non-display region on one side of the display region along the first direction; and a plurality of dummy power lines in the non-display region, the plurality of dummy power lines extending along the first direction, the plurality of dummy power lines and the plurality of dummy sub-pixels being on the same side of the display region.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate comprising a display region and a non-display region surrounding the display region;
a plurality of sub-pixels in the display region;
a plurality of power lines in the display region, the plurality of power lines extending along a first direction, and being electrically connected to the plurality of sub-pixels and being configured to provide power signals for the plurality of sub-pixels;
a plurality of dummy sub-pixels in the non-display region on one side of the display region along the first direction; and
a plurality of dummy power lines in the non-display region, the plurality of dummy power lines extending along the first direction, the plurality of dummy power lines and the plurality of dummy sub-pixels being on the same side of the display region, and at least part of the plurality of power lines being electrically connected to at least part of the plurality of dummy power lines in one-to-one correspondence;
the display substrate further comprises a plurality of first power connection lines in the non-display region, wherein the plurality of first power connection lines are disposed between the plurality of power lines and the plurality of dummy power lines and extend along the first direction, and the plurality of first power connection lines are connected to the plurality of power lines and the plurality of dummy power lines in one-to-one correspondence; and
the display substrate further comprises at least one second power connection line extending in a second direction, wherein the first direction intersects with the second direction, and the plurality of first power connection lines are at least partially overlapped with and are electrically connected to the at least one second power connection line.

2. The display substrate according to claim 1 , wherein the number of the at least one second power connection line is one, or the number of the at least one second power connection line is plural and the plurality of second power connection lines is parallel to each other.

3. The display substrate according to claim 2 , wherein the display substrate comprises one second power connection line, and a width of the second power connection line ranges from 20 microns to 30 microns in a direction perpendicular to the second direction.

4. The display substrate according to claim 1 , further comprising a plurality of pattern blocks in the non-display region, wherein the plurality of pattern blocks are spaced apart from each other around the display region.

5. The display substrate according to claim 4 , wherein orthographic projections of the first power connection line and the second power connection line on the base substrate are not overlapped with an orthographic projection of the pattern block on the base substrate.

6. The display substrate according to claim 4 , wherein the plurality of sub-pixels comprise an active layer on the base substrate, a gate layer on a side of the active layer distal from the base substrate, and a source-drain layer on a side of the gate layer distal from the base substrate;
wherein the plurality of pattern blocks are on the same layer as the active layer.

7. The display substrate according to claim 1 , further comprising a plurality of dummy data lines in the non-display region, wherein the plurality of dummy data lines extend along the first direction, and are electrically connected to the plurality of dummy power lines.

8. The display substrate according to claim 7 , wherein the plurality of dummy data lines and the plurality of dummy power lines are electrically connected in one-to-one correspondence.

9. The display substrate according to claim 8 , wherein one of the dummy data lines and one of the dummy power lines are electrically connected by a plurality of electrical contacts, wherein the plurality of electrical contacts are in one-to-one correspondence with the plurality of dummy sub-pixels.

10. The display substrate according to claim 9 , wherein the dummy sub-pixel comprises a dummy active layer on the base substrate, a first dummy gate layer on a side of the dummy active layer distal from the base substrate, and a second dummy gate layer on a side of the first dummy gate layer distal from the base substrate, wherein the dummy power line is on a side of the second dummy gate layer distal from the base substrate; and
the dummy power line is electrically connected to at least one of the dummy active layer, the first dummy gate layer, and the second dummy gate layer.

11. The display substrate according to claim 10 , wherein the dummy sub-pixel further comprises a first dummy gate insulation layer, a second dummy gate insulation layer, and a dummy interlayer insulation layer, wherein the first dummy gate insulation layer is between the dummy active layer and the first dummy gate layer, the second dummy gate insulation layer is between the first dummy gate layer and the second dummy gate layer, and the dummy interlayer insulation layer is between the second dummy gate layer and the dummy power line.

12. The display substrate according to claim 11 , wherein the dummy sub-pixel further comprises one kind of following vias:
a first via running through the second dummy gate insulation layer and the dummy interlayer insulation layer, and the dummy power line is electrically connected to the first dummy gate layer by the first via;
a second via running through the first dummy gate insulation layer, the second dummy gate insulation layer, and the dummy interlayer insulation layer, and the dummy power line is electrically connected to the dummy active layer by the second via; or
a third via running through the dummy interlayer insulation layer, and the dummy power line is electrically connected to the second dummy gate layer by the third via.

13. The display substrate according to claim 12 , wherein the dummy sub-pixel further comprises a first dummy electrode, wherein the first dummy electrode is electrically connected to the dummy power line, and is electrically connected to the dummy active layer by the second via.

14. The display substrate according to claim 12 , wherein the dummy sub-pixel further comprises a second dummy electrode, wherein the second dummy electrode is electrically connected to the dummy power line, and is electrically connected to the second dummy gate layer by the third via.

15. The display substrate according to claim 1 , further comprising a plurality of data lines in the display region, wherein the plurality of data lines extend along the first direction, and are insulated from the plurality of power lines.

16. The display substrate according to claim 1 , further comprising a power bus in the non-display region and on a side, distal to the plurality of dummy sub-pixels, of the display region, wherein the plurality of power lines are electrically connected to a flexible printed circuit (FPC) by the power bus.

17. A display device, comprising a display substrate, wherein
the display substrate comprises:
a base substrate comprising a display region and a non-display region surrounding the display region;
a plurality of sub-pixels in the display region;
a plurality of power lines in the display region, the plurality of power lines extending along a first direction, and being electrically connected to the plurality of sub-pixels and being configured to provide power signals for the plurality of sub-pixels;
a plurality of dummy sub-pixels in the non-display region on one side of the display region along the first direction; and
a plurality of d

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Meng
• Shang Tinghua
• Han Linhong
• Yang Lulu
• Qu Yi
• Zhang Xin
• He Yupeng
• Li Huijun
• Jiang Xiaofeng

Classifications

• H10K59/353

  characterised by the geometrical arrangement of the RGB subpixels · CPC title

• H10K59/88

  Dummy elements, i.e. elements having non-functional features · CPC title

• H10D86/00

  Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title