Display apparatus using semiconductor light-emitting device

Patent metadata

Field	Value
Publication number	US-12356764-B2
Application number	US-202017904506-A
Country	US
Kind code	B2
Filing date	Feb 25, 2020
Priority date	Feb 20, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A display apparatus according to the present invention comprises a substrate including semiconductor light-emitting devices and a wiring electrode electrically connected to the semiconductor light-emitting devices, wherein the substrate comprises: a base portion; assembly electrodes extending in one direction and arranged on the base portion; a dielectric layer formed to cover the assembly electrodes; a barrier portion formed on the dielectric layer while forming a cell on which the semiconductor light-emitting devices are mounted along an extension direction of the assembly electrodes; and a planarization layer formed to cover the barrier portion while forming a hole overlapping the cell, wherein the hole comprises: a first hole exposing the semiconductor light-emitting device; and a second hole exposing the dielectric layer or the base portion.

First claim

What is claimed is:

1. A display apparatus comprising:
semiconductor light-emitting devices;
a substrate comprising a wiring electrode electrically connected to the semiconductor light-emitting devices,
wherein the substrate comprises:
a base portion;
assembly electrodes disposed on the base portion and extending in one direction;
a dielectric layer positioned to cover the assembly electrodes;
a partition wall portion located on the dielectric layer and shaped to define cells, wherein the semiconductor light-emitting devices are placed on a respective cell, of the cells, along an extension direction of the assembly electrodes; and
a planarization layer positioned to cover the partition wall portion and shaped to define a first plurality of holes and a second plurality of holes that respectively overlap a cell, of the cells, and
wherein each of the first plurality of holes is shaped to expose a respective one of the semiconductor light-emitting devices; and
wherein each of the second plurality of holes is shaped to expose the dielectric layer or the base portion.

2. The display apparatus of claim 1 , wherein the wiring electrode comprises:
a lower wiring electrode located on the dielectric layer and extending in a same direction as the assembly electrodes; and
an upper wiring electrode located on the planarization layer and extending to the semiconductor light-emitting devices through a respective one of the first plurality of holes, or extending to the dielectric layer or the base portion through a respective one of the second plurality of holes.

3. The display apparatus of claim 2 , wherein the lower wiring electrode overlaps the cells and contacts a semiconductor light-emitting device, among the semiconductor light-emitting devices, placed on a respective cell, of the cells, in a region where the respective cell is located, or
the lower wiring electrode is disconnected to not overlap the cells in the region where the respective cell is located.

4. The display apparatus of claim 2 , wherein a cell, of the cells, overlaps two adjacent assembly electrodes, and
wherein the lower wiring electrode is disposed between the two adjacent assembly electrodes.

5. The display apparatus of claim 2 , wherein each of the first plurality of holes and each of the second plurality of holes have a same thickness in a width direction as that of the lower wiring electrode or thicker in the width direction than that of the lower wiring electrode.

6. A display apparatus comprising:
semiconductor light-emitting devices;
a substrate comprising a wiring electrode electrically connected to the semiconductor light-emitting devices,
wherein the substrate comprises:
a base portion;
assembly electrodes disposed on the base portion to extend in one direction;
a dielectric layer positioned to cover the assembly electrodes; and
a partition wall portion located on the dielectric layer and shaped to define cells, wherein the semiconductor light-emitting devices are placed on a respective cell, of the cells, along an extension direction of the assembly electrodes;
an organic layer that fills the cells; and
a planarization layer positioned on the organic layer and shaped to define a first plurality of holes and a second plurality of holes that respectively overlap a cell, of the cells,
wherein each of the first plurality of holes is shaped to expose a respective one of the semiconductor light-emitting devices; and
wherein each of the second plurality of holes is shaped to expose the organic layer.

7. The display apparatus of claim 6 , wherein the wiring electrode comprises:
a lower wiring electrode located on the dielectric layer and extending in a same direction as the assembly electrodes; and
an upper wiring electrode located on the planarization layer and extending to the semiconductor light-emitting devices through a respective one of the first plurality of holes, or extending to the organic layer through a respective one of the second plurality of holes.

8. The display apparatus of claim 6 , wherein a cell, of the cells, overlaps two adjacent assembly electrodes, and
wherein the lower wiring electrode is disposed between the two adjacent assembly electrodes.

9. The display apparatus of claim 6 , wherein each of the semiconductor light-emitting devices comprise:
a first conductive electrode;
a first conductive semiconductor layer disposed on the first conductive electrode;
an active layer disposed on the first conductive semiconductor layer;
a second conductive semiconductor layer disposed on the active layer; and
a second conductive electrode disposed on the second conductive semiconductor layer, and
wherein the lower wire electrode is electrically connected to the first conductive electrode, and the upper wire electrode is electrically connected to the second conductive electrode.

10. The display apparatus of claim 9 , wherein each of the semiconductor light-emitting devices comprise a passivation layer to cover a side surface of a respective one of the semiconductor light-emitting devices and a portion of the second conductive electrode.

Assignees

• Lg Electronics Inc

Inventors

• Kim Youngdo
• Kim Soohyun
• Chung Indo
• Kwon Jeonghyo
• Shin Junoh

Classifications

• H10W90/00 Primary

  Package configurations · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

• H10H20/83

  Electrodes · CPC title

• H10H20/81

  Bodies · CPC title

• H10H20/831 Primary

  characterised by their shape · CPC title