Security Verification when Resuming an RRC Connection
US-2024114334-A1 · Apr 4, 2024 · US
US12356732B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12356732-B2 |
| Application number | US-202218282146-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 17, 2022 |
| Priority date | Mar 19, 2021 |
| Publication date | Jul 8, 2025 |
| Grant date | Jul 8, 2025 |
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According to the embodiments provided herein, an island in a regular, closed shape is ablated in a first conductive layer. An interconnect is formed through the island, using the island as an alignment fiducial. The island and the interconnect are isolated from the remainder of the first conductive layer.
Opening claim text (preview).
What is claimed is: 1. A method for forming a conductive interconnection comprising: forming a semiconductor stack over a first contact; forming a first conductive layer over the semiconductor stack; and ablating a shaped region of the first conductive layer from the semiconductor stack, wherein a conductive island is formed from the first conductive layer and demarcated by the shaped region; forming a dielectric layer over the first conductive layer; forming a passage through the conductive island of the first conductive layer, the passage extending through the dielectric layer, the conductive island of the first conductive layer, and the semiconductor stack; and filling the passage, at least partially, with an interconnect that forms an electrical connection with the first contact. 2. The method of claim 1 , further comprising forming the passage such that a portion of the conductive island remains after the passage forming step. 3. The method of claim 1 , further comprising forming the passage such that the entire conductive island is removed by the passage forming step. 4. The method of claim 1 , further comprising forming the dielectric layer to partially fill the shaped region. 5. The method of claim 1 , further comprising forming a second conductive layer adjoining the dielectric layer. 6. The method of claim 5 , wherein the second conductive layer forms at least a portion of the interconnect. 7. The method of claim 1 , further comprising performing the ablating in the shape of an annular scribe ring to thereby separate and electrically isolate the conductive island from the first conductive layer. 8. The method of claim 7 , wherein the annular scribe ring is produced using a focal lens and a diffractive axicon.
Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title
Photovoltaic [PV] energy · CPC title
characterised by the shapes of the structures · CPC title
Patterning processes to connect the photovoltaic cells, e.g. laser cutting of conductive or active layers · CPC title
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