Three-dimensional NAND semiconductor memory device with intervening plug and method of manufacturing the semiconductor memory device

Patent metadata

Field	Value
Publication number	US-12356606-B2
Application number	US-202217825873-A
Country	US
Kind code	B2
Filing date	May 26, 2022
Priority date	Oct 26, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

The present technology includes a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a first stack structure over a lower structure in which a cell region and a slimming region are defined, including a plurality of first gate lines, a first interlayer insulating structure over the first stack structure, a second stack structure over the first interlayer insulating structure, and a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure and the second stack structure in the cell region.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a first stack structure over a lower structure in which a cell region and a slimming region are defined, including first gate lines;
a second stack structure over the first stack structure, including second gate lines;
a first interlayer insulating structure disposed between the first stack structure and the second stack structure;
and
a plurality of vertical plugs passing through the first stack structure, the first interlayer insulating structure, and the second stack structure in the cell region,
wherein the first gate lines include first end portions, respectively,
wherein the second gate lines include second end portions, respectively,
wherein the first interlayer insulating structure includes a third end portion, which is not overlapped with the first and second end portions, and
wherein the first to third end portions have a step shape.

2. The semiconductor memory device of claim 1 , wherein the upper surfaces and side surfaces of the first to third end portions have the step shape.

3. The semiconductor memory device of claim 1 , further comprising a second interlayer insulating structure disposed between the first interlayer insulating structure and the second stack structure.

4. The semiconductor memory device of claim 3 , wherein the second interlayer insulating structure includes a fourth end portion, which is not overlapped with the first to third end portions.

5. The semiconductor memory device of claim 3 , further comprising:
interlayer insulating layers formed between the first gate lines and between the second gate lines.

6. The semiconductor memory device of claim 5 , wherein the first interlayer insulating structure and the second interlayer insulating structure are formed of a layer of the same material as the interlayer insulating layers, and
wherein an edge of the first stack structure and the second stack structure formed in the slimming region are formed in a step shape.

7. The semiconductor memory device of claim 5 , wherein the first and the second interlayer insulating structure are thicker than each of the interlayer insulating layers.

8. The semiconductor memory device of claim 4 , wherein a height and a distance of the third end portion is different from a height and a distance of each of the first end portions.

9. The semiconductor memory device of claim 1 , wherein each of the vertical plugs includes a memory layer, a channel layer, and a vertical insulating layer sequentially formed along an inner wall of vertical holes vertically passing through the first stack structure and the second stack structure.

10. The semiconductor memory device of claim 1 , wherein the first to third end portions are disposed in the slimming region.

11. The semiconductor memory device of claim 3 , further comprising:
a third interlayer insulating structure formed between the first interlayer insulating structure and the second interlayer insulating structure.

12. The semiconductor memory device of claim 11 , wherein the third interlayer insulating structure is thicker than each of interlayer insulating layers.

13. The semiconductor memory device of claim 11 , wherein each of the vertical plugs further includes a third vertical plug formed in a portion passing through the third interlayer insulating structure.

14. The semiconductor memory device of claim 13 , wherein the third vertical plug connects a first portion and a second portion of channel layer included in the each of the vertical plugs;
wherein the first portion is passing through the first stack structure and the first interlayer insulating structure; and
wherein the second portion is passing through the second stack structure and the second interlayer insulating structure.

15. The semiconductor memory device of claim 1 , wherein each of the vertical plugs comprises:
a memory layer formed along an inner wall of a vertical hole, the vertical hole vertically passing through the first stack structure and the second stack structure;
a channel layer formed along an inner wall of the memory layer;
a vertical insulating layer formed in a region surrounded by the channel layer; and
a vertical channel separation structure vertically separating the vertical insulating layer, the channel layer, and the memory layer in a vertical direction.

Assignees

• Sk Hynix Inc

Inventors

• Choi Won Geun
• Kim Jang Won
• Jang Jung Shik

Classifications

• H10B12/0335

  Making a connection between the transistor and the capacitor, e.g. plug · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B43/50

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title