Image sensor with a control circuit

Patent metadata

Field	Value
Publication number	US-12356101-B2
Application number	US-202217885960-A
Country	US
Kind code	B2
Filing date	Aug 11, 2022
Priority date	Aug 31, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

An image sensor includes an array of pixels inside and on top of a substrate. A control circuit is configured to apply voltage potentials to the substrate. During a first phase, the control circuit applies a ground potential to the substrate. During a second phase, the control circuit applies a potential positive with respect to the ground potential to the substrate.

First claim

The invention claimed is:

1. An image sensor, comprising:
an array of pixels inside and on top of a substrate; and
a control circuit configured to:
apply a first potential at ground to the substrate during a first phase of pixel operation for reading charge from the pixel; and
apply a second potential to the substrate that is positive with respect to the first potential during a second phase of pixel operation for integrating charge in the pixel;

wherein each pixel comprises:
a first area configured to generate charge in response to a luminous excitation; and
at least two circuit assemblies, wherein each circuit assembly comprises:
a second area configured to storing charge generated by the first area; and
a first transfer gate configured to controlling a transfer of the charge from the first area to the second area;

wherein the control circuit is configured to control, for each transfer gate of each circuit assembly of each pixel:
a setting of the first transfer gate to a conductive state by applying a third potential, and
a setting of the first transfer gate to a non-conductive state by applying a fourth potential smaller than the third potential:

wherein the second potential is controlled so that the first transfer gate is non-conductive when the second potential is applied to the substrate and the fourth potential is applied to the first transfer gate, the fourth potential being equal to or smaller than a potential of the substrate.

2. The image sensor according to claim 1 , wherein the control circuit is configured to lower the fourth potential between the second phase and the first phase.

3. The image sensor according to claim 1 :
wherein charge integrated in the second phase by the first area are transferred and stored in at least one of said second areas; and
wherein charge read in the first phase corresponds to reading a state representative of the charge stored at the second areas.

4. The image sensor according to claim 1 , wherein the image sensor is of indirect time of flight type.

5. An image sensor comprising:
an array of pixels inside and on top of a substrate; and
a control circuit configured to:
apply a first potential at ground to the substrate during a first phase of pixel operation for reading charge from the pixel; and

apply a second potential to the substrate that is positive with respect to the first potential during a second phase of pixel operation for integrating charge in the pixel;
wherein each pixel comprises:
a first area configured to generate charge in response to a luminous excitation; and
at least two circuit assemblies, wherein each circuit assembly comprises:
a second area configured to storing charge generated by the first area; and
a first transfer gate configured to controlling a transfer of the charge from the first area to the second area;

wherein each pixel comprises a second circuit coupling the at least two circuit assemblies to at least one conductive line, the second circuit comprising a second transfer gate driven by the control circuit and configured to transfer charge stored at the second area towards a sense node; and
wherein the control circuit is configured to lower a fifth potential applied to the second transfer gate by a value of the second potential between the second phase and the first phase.

6. The image sensor according to claim 5 , wherein the second circuit comprises:
a first transistor having its drain coupled to the sense node;
a second transistor having a control gate coupled to the sense node; and
a third transistor connected between the conductive line and a source of the second transistor;
wherein the control circuit is configured to lower, between the second phase and the first phase:
a sixth potential applied to the second transfer gate by the value of the second potential; and
a seventh potential and an eighth potential for controlling the first transistor by the value of the second potential.

7. An image sensor comprising:
an array of pixels inside and on top of a substrate; and
a control circuit configured to:
apply a first potential at ground to the substrate during a first phase of pixel operation for reading charge from the pixel; and
apply a second potential to the substrate that is positive with respect to the first potential during a second phase of pixel operation for integrating charge in the pixel;

wherein each pixel comprises:
a first area configured to generate charge in response to a luminous excitation; and
at least two circuit assemblies, wherein each circuit assembly comprises:
a second area configured to storing charge generated by the first area; and
a first transfer gate configured to controlling a transfer of the charge from the first area to the second area;

wherein the control circuit comprises:
a fourth transistor controlled independently of a fifth transistor;
wherein a drain of the fourth transistor is coupled to a drain of the fifth transistor at a second node;
wherein a source of the fourth transistor is further coupled to a power supply voltage rail;
wherein a source of the fifth transistor is further coupled to ground;
a first switch connected between the second node and a fourth node;
a second switch connected between the ground and the fourth node;
a second capacitive element connected between a third node and the fourth node;
a voltage source configured to delivering the second potential;
wherein the voltage source is connected between the ground and a third switch, said third switch being connected between the voltage source and the third node; and
a fourth switch connected between the ground and the third node;
wherein the first transfer gate is coupled to the second node.

8. The image sensor according to claim 7 , wherein between the second phase and the first phase:
the fourth transistor and the fifth transistor are driven so that the fourth transistor is in a non-conductive state and the fifth transistor is in a conductive state;
then the fourth transistor and the fifth transistor are driven independently to be in a non-conductive state;
then the third switch is set to a non-conductive state;
then the second switch is set to a non-conductive state; and
then the first and fourth switches are set to a conductive state.

9. The image sensor according to claim 8 , wherein the first phase and the second phase are alternated in time, and wherein, between the first phase and the second phase:
the first and fourth switches are set to a non-conductive state;
then the second switch is set to a conductive state;
then the third switch is set to a conductive state; and
then the fourth transistor and the fifth transistor are driven to be alternately conductive.

10. An image sensor, comprising:
a matrix of pixels in and on a substrate, each pixel comprising a first zone configured to generate charge from light excitation and a memory zone configured to store charges generated by the first zone; and
a control circuit configured to:
apply a first potential at ground to the substrate during a first phase and control during the first phase turn off of a transistor for transferring charges to the memory zone with a control signal at a first voltage lower than ground; and
apply a second potential to the substrate that is positive with respect to the first potential during a second phase and control during the second phase turn off of the transistor for transferring charges to the memory zone with the control signal at a second voltage at ground;

wherein the second phase is an integration phase during which charge generated by the first zone of each pixel is transferred and stored in the memory zone of said pixel; and

Assignees

• St Microelectronics Grenoble 2
• St Microelectronics Crolles 2 Sas

Inventors

• Simony Laurent
• Lalanne Frederic

Classifications

• H10F39/80373

  characterised by the gate of the transistor · CPC title

• H10F39/8023

  Disposition of the elements in pixels, e.g. smaller elements in the centre of the imager compared to larger elements at the periphery · CPC title

• H10F39/812

  Arrangements for transferring the charges in the image sensor perpendicular to the imaging plane, e.g. buried regions used to transfer generated charges to circuitry under the photosensitive region · CPC title

• H04N25/779

  Circuitry for scanning or addressing the pixel array · CPC title

• H04N25/771

  comprising storage means other than floating diffusion · CPC title