Programmable RF front end for wideband ADC-based receiver

Patent metadata

Field	Value
Publication number	US-12355478-B2
Application number	US-202217568801-A
Country	US
Kind code	B2
Filing date	Jan 5, 2022
Priority date	Jan 27, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A receiver includes an antenna block configured to transduce impinging electromagnetic signals into electrical signals; a signal conditioning block configured to condition electrical signals received from the antenna block; and a down-converter block configured to down-convert conditioned electrical signals received from the signal conditioning block. The down-converter block comprises a plurality of signal channels. The receiver further includes a plurality of analog-to-digital converters (ADCs) respectively connected to the signal channels of the down-converter block; and a field-programmable gate array (FPGA). The FPGA is configured to program the down-converter block by selecting a set of mixer frequencies and a set of bandwidths designed to remove interference signals in each signal channel. The selections are calculated to mitigate reductions in dynamic range in the ADCs due to interference. The FPGA is further configured to process digital signals received from the ADCs after the down-converter block has removed the interference signals.

First claim

The invention claimed is:

1. A receiver comprising:
an antenna block configured to transduce impinging electromagnetic signals into electrical signals;
a signal conditioning block connected and configured to condition electrical signals received from the antenna block;
a down-converter block connected and configured to down-convert conditioned electrical signals received from the signal conditioning block, the down-converter block comprising a plurality of signal channels, wherein each signal channel comprises a respective mixer having an output, a respective switch filter connected to the output of the respective mixer, and a respective down-conversion mixer directly connected to an output of the respective switch filter;
a plurality of programmable frequency synthesizers respectively connected to the mixers the plurality of signal channels of the down-converter block;
a plurality of analog-to-digital converters (ADCs) respectively connected to the plurality of signal channels of the down-converter block; and
a field-programmable gate array (FPGA) connected to the plurality of ADCs, to the plurality of frequency synthesizers, and to the switch filters of the plurality of signal channels of the down-converter block, wherein the FPGA is configured to perform operations comprising:
commanding a frequency search over signals coming into the plurality of ADCs in order to derive interference frequencies of interference signals;
programming the down-converter block by selecting a set of mixer frequencies to be respectively sent to the plurality of frequency synthesizers and a set of bandwidths to be respectively sent to the switch filters, the set of mixer frequencies and the set of bandwidths being designed to remove the interference signals having respective interference frequencies in each signal channel, the selections being calculated to mitigate reductions in dynamic range in the plurality of ADCs due to the interference signals; and
processing digital signals received from the plurality of ADCs after the down-converter block has removed the interference signals.

2. The receiver as recited in claim 1 , wherein the plurality of ADCs have respective adjacent narrow bandwidths that cover a wider bandwidth, the FPGA being configured to select mixer frequencies and bandwidths that enable the down-converter block to fit down-converted signals within the respective bandwidths of the ADCs.

3. The receiver as recited in claim 1 , wherein programming the down-converter block comprises outputting respective filter selection logic signals to each switch filter of the switch filters.

4. The receiver as recited in claim 3 , wherein each switch filter comprises:
a first switch connected to the respective mixer, the first switch being configured to change from a first state to a second state in response to receipt of a first filter selection logic signal by the respective switch filter;
a second switch connected to the respective down-conversion mixer, the second switch being configured to change from a first state to a second state in response to receipt of the first filter selection logic signal by the switch filter;
a first bandpass filter having a first bandwidth, the first bandpass filter connecting the second switch to the first switch when the first and second switches are in the first states; and
a second bandpass filter having a second bandwidth, the second bandpass filter connecting the second switch to the first switch when the first and second switches are in the second states.

5. The receiver as recited in claim 4 , wherein:
the first switch is further configured to change from the first state to a third state in response to receipt of a second filter selection logic signal by the switch filter;
the second switch is further configured to change from the first state to a third state in response to receipt of the second filter selection logic signal by the switch filter; and
the switch filter further comprises a third bandpass filter having a third bandwidth, the third bandpass filter connecting the second switch to the first switch when the first switch and the second switch are in the third states.

6. The receiver as recited in claim 4 , wherein the plurality of programmable frequency synthesizers are connected and configured to provide respective oscillator signals having selected mixer frequencies to the mixers of the plurality of signal channels of the down-converter block, wherein programming the down-converter block comprises outputting respective mixer frequency selection logic signals representing the selected mixer frequencies from the FPGA to the programmable frequency synthesizers.

7. The receiver as recited in claim 4 , further comprising a local oscillator and a splitter having an input terminal connected to the local oscillator and a plurality of output terminals respectively connected to the respective down-conversion mixers of the down-converter block.

8. The receiver as recited in claim 3 , wherein each signal channel of the down-converter block further comprises a low-pass filter connected to the down- conversion mixer and an amplifier connected to the low-pass filter and to a respective ADC of the plurality of ADCs.

9. The receiver as recited in claim 1 , wherein the FPGA is configured to execute an interference reduction algorithm which is configured to generate filter selection logic signals and mixer frequency selection logic signals in dependence on the interference frequencies of detected interference signals.

10. The receiver as recited in claim 9 , wherein the interference reduction algorithm solves a bin packing problem.

11. The receiver as recited in claim 1 , wherein the FPGA is further configured to determine the interference frequencies of detected interference signals from internal measurements.

12. The receiver as recited in claim 1 , wherein processing digital signals received from the plurality of ADCs comprises searching for radar signals and then outputting descriptions of each detected radar signal.

13. The receiver as recited in claim 1 , wherein processing digital signals received from the plurality of ADCs comprises detecting and demodulating a single extremely broadband communication signal that covers an entire bandwidth of the ADCs.

14. The receiver as recited in claim 1 , wherein the signal conditioning block comprises:
a wideband amplifier;
a splitter having an input terminal connected to the wideband amplifier and a plurality of output terminals; and
a plurality of signals channels respectively connecting the plurality of output terminals of the splitter to the plurality of signals channels of the down-converter block.

15. A method for processing signals from an antenna using a plurality of signal channels respectively connected to a plurality of analog-to-digital converters (ADCs), the signals being processed by a field-programmable gate array (FPGA) connected to the plurality of ADCs, the method being performed by the FPGA and comprising:
(a) commanding a frequency search over signals coming into the plurality of ADCs in order to derive interference frequencies of interference signals;
(b) executing an interference reduction algorithm that selects a set of mixer frequencies and a set of bandwidths designed to remove the interference signals in each signal channel of the plurality of signal channels, the selections being calculated to mitigate reductions in dynamic range in the plurality of ADCs due to the interference signals,
wherein a respective filter selection logic signal is generated and transmitted to a respective switch filter of a down-converter blo

Assignees

• Boeing Co

Inventors

• Ray Gary A
• Adams Alec

Classifications

• H04B1/0078

  with a common intermediate frequency amplifier for the different intermediate frequencies, e.g. when using switched intermediate frequency filters · CPC title

• H04B1/0096

  where a full band is frequency converted into another full band · CPC title

• H04B2001/307

  using n-port mixer · CPC title

• H04B1/10

  Means associated with receiver for limiting or suppressing noise or interference · CPC title

• H04B1/30 Primary

  for homodyne or synchrodyne receivers (demodulator circuits H03D1/22) · CPC title