Display substrate, manufacturing method thereof, and display apparatus

Patent metadata

Field	Value
Publication number	US-12354915-B2
Application number	US-202117769809-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	Apr 29, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Embodiments of the disclosure disclose a display substrate, a manufacturing method thereof and a display apparatus. The display substrate includes: a base, having a wire routing region; a first wire routing layer, located on the base, where the first wire routing layer in the wire routing region includes a plurality of first routing wires arranged at intervals, and a space between adjacent first routing wires is smaller than 2 um; an insulation layer, located on a side of the first wire routing layer facing away from the base and having a plurality of first via holes corresponding to the first routing wires; a first flat layer, located on a side of the insulation layer facing away from the base and having second via holes corresponding to the first via holes, where the second via holes at least partially overlap with the first via holes.

First claim

What is claimed is:

1. A display substrate, comprising:
a base, having a wire routing region;
a first wire routing layer, located on the base, wherein the first wire routing layer in the wire routing region comprises a plurality of first routing wires arranged at intervals, and a space between adjacent first routing wires is smaller than 2 μm;
an insulation layer, located on a side of the first wire routing layer facing away from the base and having a plurality of first via holes corresponding to the first routing wires; and
a first flat layer, located on a side of the insulation layer facing away from the base and having second via holes corresponding to the first via holes, wherein the second via holes at least partially overlap with the first via holes;
wherein the insulation layer comprises a plurality of independent sub-insulation layers corresponding to the first routing wires, the sub-insulation layers have the first via holes, and a wire width of each of the first routing wires is smaller than or equal to 2 μm.

2. The display substrate according to claim 1 , wherein the space between adjacent first routing wires is 0.8 μm to 1.8 μm, and the wire width of each of the first routing wires is 1.0 μm to 1.8 μm.

3. The display substrate according to claim 1 , comprising a display region and a bezel region, wherein the display region comprises a first display region and a second display region, and light transmittance of the first display region is larger than light transmittance of the second display region;
the first display region comprises a plurality of sub-pixels distributed in an array, wherein the sub-pixels comprise light-emitting devices and a pixel circuit, the pixel circuit is located in the bezel region adjacent to the first display region, or the second display region has a transition region adjacent to the first display region, and the pixel circuit is located in the transition region;
the wire routing region is at least partially located in the first display region, and the first wire routing layer is located between anodes of the light-emitting devices and the pixel circuit; and
the first routing wires are electrically connected with the anodes of the light-emitting devices through corresponding first via holes and corresponding second via holes.

4. The display substrate according to claim 3 , further comprising a second flat layer located between the pixel circuit and the first wire routing layer, wherein the second flat layer has a plurality of fourth via holes corresponding to the first routing wires; and
the first routing wires are electrically connected with the pixel circuit through corresponding fourth via holes.

5. The display substrate according to claim 1 , comprising a display region and a bezel region, wherein the display region comprises a plurality of signal lines, and the bezel region comprises the wire routing region; and
the first routing wires are configured to be electrically connected with corresponding signal lines.

6. The display substrate according to claim 1 , further comprising a second wire routing layer located between the insulation layer and the first flat layer, wherein the second wire routing layer in the wire routing region comprises a plurality of second routing wires arranged at intervals; and
grooves are defined by the insulation layer between the adjacent first routing wires, and the second routing wires are at least located in the grooves.

7. The display substrate according to claim 6 , wherein a width of an orthographic projection of each of the second routing wires on the base is smaller than a width of an orthographic projection of the insulation layer between adjacent first via holes on the base.

8. The display substrate according to claim 7 , wherein the orthographic projection of each of the second routing wires on the base approximately overlaps with an orthographic projection of a space between the adjacent first routing wires on the base.

9. The display substrate according to claim 7 , wherein a width of each of the first routing wires is larger than or equal to 1.5 μm and smaller than 2 μm, and a maximum width of each of the first via holes is larger than or equal to 1.1 μm and smaller than 1.6 μm; and
an orthographic projection of each of the first routing wires on the base has a first annular side edge, an orthographic projection of each of the first via holes on the base has a second annular side edge, and a space between the first annular side edge and the second annular side edge is larger than or equal to 0.2 μm.

10. The display substrate according to claim 6 , wherein the first flat layer has third via holes corresponding to the second routing wires.

11. The display substrate according to claim 6 , wherein a sum of a thickness of the second routing wires and a thickness of the insulation layer is approximately equal to a thickness of the first routing wires.

12. The display substrate according to claim 6 , comprising a display region and a bezel region, wherein the display region comprises a first display region and a second display region, and light transmittance of the first display region is larger than light transmittance of the second display region;
the first display region comprises a plurality of sub-pixels distributed in an array, the sub-pixels comprise light-emitting devices and a pixel circuit, the pixel circuit is located in the bezel region adjacent to the first display region, or the second display region has a transition region adjacent to the first display region, and the pixel circuit is located in the transition region;
the wire routing region is at least partially located in the first display region, and the first wire routing layer and the second wire routing layer are located between the light-emitting devices and the pixel circuit; and
the first routing wires are electrically connected with anodes of the light-emitting devices through corresponding first via holes and corresponding second via holes, and the second routing wires are electrically connected with the anodes of the light-emitting devices through corresponding third via holes.

13. The display substrate according to claim 12 , further comprising a second flat layer located between the pixel circuit and the first wire routing layer, wherein the second flat layer has a plurality of fourth via holes corresponding to the first routing wires and the second routing wires, and the insulation layer has fifth via holes corresponding to the second routing wires; and
the first routing wires are electrically connected with the pixel circuit through corresponding fourth via holes, and the second routing wires are electrically connected with the pixel circuit through corresponding fourth via holes and corresponding fifth via holes.

14. The display substrate according to claim 6 , comprising a display region and a bezel region, the display region comprises a plurality of signal lines, and the bezel region comprises the wire routing region; and
the first routing wires are configured to be electrically connected with corresponding signal lines, and the second routing wires are configured to be electrically connected with corresponding signal lines.

15. The display substrate according to claim 1 , wherein the thickness of the insulation layer is 700 Å to 800 Å.

16. A manufacturing method of the display substrate according to claim 1 , comprising:
providing the base, wherein the base has a wire routing region;
forming the first wire routing layer and the insulation layer on the base, wherein the first wire routing layer in the wire routing region

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Song Liang
• Jiang Long
• Wang Mingwen
• Liao Pengyu
• Lu Zhong
• Xu Yuanjie
• Wang Benlian
• Du Lili
• Jiang Donghua

Classifications

• H10D84/01 Primary

  Manufacture or treatment · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H01L21/77 Primary

  Electricity · mapped topic