Element forming wafer and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12354875-B2
Application number	US-202217732688-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	Nov 20, 2019
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A method for manufacturing an element forming wafer includes the steps of: forming a thin layer on a semiconductor wafer having a plurality of chip forming regions; and adjusting stress generated in an element forming portion of the thin layer to have a specified value. The thin layer constitutes an element in each of the plurality of chip forming regions. The step of adjusting the stress includes: arranging a resist on the thin layer; exposing the resist to light using a photomask having openings; forming openings in the resist by developing the resist; and performing ion-implantation using the resist as a mask. The photomask used during the step of exposing the resist to light has a ratio of the openings that is adjusted based on the stress generated in the element forming portion.

First claim

The invention claimed is:

1. An element forming wafer, comprising:
a semiconductor wafer having a plurality of chip forming regions; and
a thin layer formed on the semiconductor wafer, wherein
a plurality of portions of the thin layer each of which forms an element in each of the plurality of chip forming portions are defined as a plurality of element forming portions,
a plurality of regions are formed in the thin layer in one direction that passes through a center of the semiconductor wafer and that extends along an in-plane direction of the semiconductor wafer,
each of the plurality of element forming portions is arranged in a respective one of the plurality of regions,
a stress distribution that is along the one direction and is generated across the plurality of element forming portions has a maximum and a minimum of the stress in each of the plurality of regions, and
a rate of change in the stress between the maximum and the minimum in each of the plurality of regions is smaller than a rate of change in the stress at a boundary between adjacent ones of the plurality of regions.

2. The element forming wafer according to claim 1 , wherein
the thin layer is formed of a piezoelectric layer, and
the piezoelectric layer has an implantation region into which an element having a same group number as that of an element constituting the piezoelectric layer is implanted.

Assignees

• Denso Corp

Inventors

• Teshigahara Akihiko
• Suzuki Megumi

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10P30/22 Primary

  using masks · CPC title

• H10N39/00

  Integrated devices, or assemblies of multiple devices, comprising at least one piezoelectric, electrostrictive or magnetostrictive element covered by groups H10N30/00 – H10N35/00 · CPC title

• H10N30/074

  by depositing piezoelectric or electrostrictive layers, e.g. aerosol or screen printing · CPC title

• H10N30/704

  based on piezoelectric or electrostrictive films or coatings · CPC title