Multilayer stacking wafer bonding structure and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-12354870-B2
Application number	US-202318097285-A
Country	US
Kind code	B2
Filing date	Jan 16, 2023
Priority date	Nov 14, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A multilayer stacking wafer bonding structure is provided in the present invention, including a logic wafer with a substrate and a logic circuit layer on the substrate, multiple memory wafers bonded sequentially on the logic circuit layer to form a first multilayer stacking structure, wherein each memory wafer includes a memory layer, a silicon layer on the memory layer and multiple oxide layers in trenches of the silicon layer, and the oxide layers in the memory wafers are aligned each other in a direction vertical to the substrate, and multiple through-oxide vias (TOV) extending through the memory layers and the oxide layers in the first multilayer stacking structure into the logic circuit layer, and the TOVs do not extend through any of the silicon layers.

First claim

What is claimed is:

1. A multilayer stacking wafer bonding structure, comprising:
a logic wafer with a substrate and a logic circuit layer on said substrate;
multiple memory wafers stacked and bonded sequentially on said logic circuit layer of said logic wafer to constitute a first multilayer stacking structure, wherein each of said memory wafers comprises a memory layer, a silicon layer on said memory layer and multiple oxide layers in trenches of said silicon layer and connecting with said memory layer, and surfaces of said oxide layers and said silicon layer are flush, and said oxide layers in said memory wafers are aligned with each other in a direction vertical to said substrate;
multiple through-oxide vias (TOVs) extending through all of said memory layers and said oxide layers in said first multilayer stacking structure to said logic circuit layer of said logic wafer, and said TOVs do not extend through any of said silicon layers in said memory wafers; and
semiconductor via middle through-silicon vias (TSVs) in said logic wafer and connected with corresponding said TOVs.

2. The multilayer stacking wafer bonding structure of claim 1 , further comprising oxide bonding layers on parts of surface of said memory wafer, and each of said oxide bonding layers bonds two adjacent said memory wafers.

3. The multilayer stacking wafer bonding structure of claim 1 , further comprising a second multilayer stacking structure bonded on said first multilayer stacking structure, and said second multilayer stacking structure is provided with the same said memory layers, said silicon layers, said oxide layers and said TOVs as the ones of said first multilayer stacking structure, and said TOVs in said second multilayer stacking structure are connected with said TOVs in said first multilayer stacking structure.

4. The multilayer stacking wafer bonding structure of claim 1 , further comprising a redistribution layer on a surface of outermost said memory wafer and connected with said TOVs, and a material of said redistribution layer is copper (Cu).

5. The multilayer stacking wafer bonding structure of claim 4 , further comprising:
multiple bonding pads on and connected with said redistribution layer, and a material of said bonding pads is aluminum (Al); and
a passivation layer on and exposing said bonding pads.

6. The multilayer stacking wafer bonding structure of claim 1 , wherein surfaces of said TOVs are provided with barrier layers, and a material of said TOVs is tungsten (W), and a material of said barrier layers is titanium (Ti), tantalum (Ta) or tantalum nitride (TaN).

7. The multilayer stacking wafer bonding structure of claim 1 , wherein said first multilayer stacking structure is provided with at least four said memory wafers.

8. The multilayer stacking wafer bonding structure of claim 1 , wherein one side of each of said memory wafers close to said memory layer is front side, and the other side of each of said memory wafers close to said silicon layer and said oxide layer is back side, and said memory wafers are stacked and bonded individually in a way of said front side to said front side, said front side to said back side, or said back side to said back side.

9. The multilayer stacking wafer bonding structure of claim 1 , wherein one side of said logic wafer close to said logic circuit layer is front side, and the other side of said logic wafer close to said substrate is back side, and said logic wafer is bonded with said first multilayer stacking structure using said front side or said back side.

10. A method of manufacturing a multilayer stacking wafer bonding structure, comprising:
providing a logic wafer, wherein said logic wafer comprises a first substrate and a logic circuit layer on said substrate;
providing a memory wafer, wherein said memory wafer comprises a second substrate, multiple oxide layers in trenches of said second substrate and a memory layer on surfaces of said second substrate and said oxide layers;
bonding said memory layer of said memory wafer with said logic circuit layer of said logic wafer;
performing a backside grinding step to remove parts of said second substrate, so that said second substrate becomes a silicon layer and said oxide layers are exposed from said silicon layer, and surfaces of said oxide layers and said silicon layer are flush;
repeating aforementioned steps of providing said memory wafers and backside grinding process to sequentially stack and bond multiple memory wafers on said logic wafer to constitute a first multilayer stacking structure, wherein said oxide layers in said memory wafers are aligned with each other in a direction vertical to said first substrate;
performing a photolithography process to form multiple first through-oxide via (TOV) holes, wherein said first TOV holes extend through all of said memory layers and said oxide layers in said first multilayer stacking structure to said logic circuit layer of said logic wafer, and said first TOV holes do not extend through any of said silicon layers in said memory wafers;
filling said first TOV holes with conductive materials to form first TOVs; and
forming via middle through-silicon vias (TSVs) in said logic wafer after said memory wafers are bonded, and said first TOVs formed in later process are connected with corresponding said via middle TSVs.

11. The method of manufacturing a multilayer stacking wafer bonding structure of claim 10 , further comprising:
forming oxide bonding layers on surfaces of said memory wafers; and
bonding adjacent said memory wafers through said oxide bonding layers.

12. The method of manufacturing a multilayer stacking wafer bonding structure of claim 10 , further comprising:
providing a second multilayer stacking structure, wherein said second multilayer stacking structure is provided with the same said memory layers, said silicon layers, said oxide layers and said TOVs as the ones of said first multilayer stacking structure;
bonding said second multilayer stacking structure with said first multilayer stacking structure, wherein said oxide layers in said second multilayer stacking structure are aligned with said oxide layers in said first multilayer stacking structure in a direction vertical to said first substrate and said second substrate;
performing another photolithography process to form multiple second TOV holes, wherein said second TOV holes extend through all of said memory layers and said oxide layers in said second multilayer stacking structure and expose corresponding said first TOVs in said first multilayer stacking structure; and
filling said second TOV holes with conductive materials to form second TOVs, and said second TOVs are connected with corresponding said first TOVs.

13. The method of manufacturing a multilayer stacking wafer bonding structure of claim 10 , further comprising forming a redistribution layer on a surface of outermost said memory wafer, and said redistribution layer is connected with said first TOVs.

14. The method of manufacturing a multilayer stacking wafer bonding structure of claim 13 , further comprising:
forming multiple bonding pads on said redistribution layer, and said bonding pads are connected with said redistribution layer; and
forming a passivation layer on and exposing said bonding pads.

Assignees

• Powerchip Semiconductor Mfg Corp

Inventors

• Chang Shou-Zen
• Lu Chun-Lin

Classifications

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/9232

  with additional elements interposed between layers · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title

• H10P14/6939

  characterised by the metal · CPC title