Display device

Patent metadata

Field	Value
Publication number	US-12354521-B2
Application number	US-202318457318-A
Country	US
Kind code	B2
Filing date	Aug 28, 2023
Priority date	Sep 27, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A display device including a display panel is disclosed. The display panel includes a substrate, multiple scan lines, multiple data lines, multiple pixel structures, a first gate driving circuit, and a second gate driving circuit. The pixel structures are electrically connected to the scan lines and the data lines. Multiple first output stage circuits of the first gate driving circuit disposed in a peripheral area are electrically connected to the scan lines. Multiple second output stage circuits of the second gate driving circuit disposed in the peripheral area are electrically connected to the scan lines. A channel width of a first output transistor of the first output stage circuit is greater than a channel width of a second output transistor of the second output stage circuit.

First claim

What is claimed is:

1. A display device, comprising a display panel, wherein the display panel comprises:
a substrate, provided with a display area and a peripheral area outside the display area;
a plurality of scan lines and a plurality of data lines, disposed in the display area;
a plurality of pixel structures, disposed in the display area, and electrically connected to the plurality of scan lines and the plurality of data lines;
a first gate driving circuit, disposed in the peripheral area and comprising a plurality of first output stage circuits, wherein the plurality of first output stage circuits are electrically connected to the plurality of scan lines, and the first gate driving circuit is located on a first side of the display area;
a second gate driving circuit, disposed in the peripheral area and comprising a plurality of second output stage circuits, wherein the plurality of second output stage circuits are electrically connected to the plurality of scan lines, and the second gate driving circuit is located on a second side of the display area; and
another gate driving circuit, disposed in the peripheral area and comprising a plurality of another output stage circuits, wherein the plurality of another output stage circuits are electrically connected to the plurality of scan lines, and the another gate driving circuit is located on a third side of the display area,
wherein the plurality of first output stage circuits respectively have a first output transistor, the plurality of second output stage circuits respectively have a second output transistor, and a channel width of the first output transistor is greater than a channel width of the second output transistor, when the display panel is driven at a first frame rate, the plurality of first output stage circuits output a plurality of first gate driving signals to the plurality of scan lines; when the display panel is driven at a second frame rate, the plurality of second output stage circuits output a plurality of second gate driving signals to the plurality of scan lines, wherein the first frame rate is greater than the second frame rate,
wherein the another gate driving circuit is a third gate driving circuit, the plurality of another output stage circuits are a plurality of third output stage circuits, and the plurality of third output stage circuits are electrically connected to the plurality of scan lines,
wherein the plurality of third output stage circuits respectively have a third output transistor, and a channel width of the third output transistor is smaller than the channel width of the second output transistor.

2. The display device according to claim 1 , wherein the display panel further comprises a plurality of first clock signal lines and a plurality of second clock signal lines disposed in the peripheral area, wherein the plurality of first output stage circuits are electrically connected to the plurality of first clock signal lines, the plurality of second output stage circuits are electrically connected to the plurality of second clock signal lines, the plurality of first clock signal lines are adapted to transmit a plurality of first clock signals to the plurality of first output stage circuits, the plurality of second clock signal lines are adapted to transmit a plurality of second clock signals to the plurality of second output stage circuits, and a frequency of each of the first clock signals is greater than a frequency of each of the second clock signals.

3. The display device according to claim 1 , wherein when the display panel is driven at a third frame rate, the plurality of third output stage circuits output a plurality of third gate driving signals to the plurality of scan lines, wherein the second frame rate is greater than the third frame rate.

4. The display device according to claim 1 , wherein the second side is adjacent to the first side, and the third side is adjacent to the second side and opposite to the first side.

5. The display device according to claim 4 , wherein the display panel further comprises:
a plurality of auxiliary signal lines, electrically connected to the second gate driving circuit, and each of the scan line is electrically connected to a corresponding one of the plurality of auxiliary signal lines.

6. The display device according to claim 5 , wherein each of the pixel structure comprises:
a pixel transistor, electrically connected to one of the scan lines and one of the data lines;
a pixel electrode, electrically connected to the pixel transistor; and
a common electrode, overlapping the pixel electrode, wherein the plurality of auxiliary signal lines are electrically connected to the plurality of scan lines through a plurality of conductive patterns, and one of the pixel electrode and the common electrode is of a same film layer as the plurality of conductive patterns.

7. The display device according to claim 5 , wherein the plurality of scan lines belong to a first metal layer, the plurality of auxiliary signal lines belong to a second metal layer, and the display panel further comprises:
an insulating layer, located between the first metal layer and the second metal layer, and the insulating layer has a plurality of through holes,
wherein each of the auxiliary signal lines is electrically connected to a corresponding one of the scan lines through a corresponding one of the through holes.

8. The display device according to claim 1 , wherein the display panel further comprises:
a plurality of first clock signal lines and a plurality of second clock signal lines disposed in the peripheral area, wherein the plurality of first output stage circuits are electrically connected to the plurality of first clock signal lines, and the plurality of second output stage circuits are electrically connected to the plurality of second clock signal lines, and the display device further comprises:
a driving chip, disposed on the substrate and located in the peripheral area, wherein the driving chip has a plurality of first signal pins, a plurality of second signal pins, and a plurality of third signal pins, the plurality of first clock signal lines are electrically coupled to the first signal pins, the plurality of second clock signal lines are electrically coupled to the second signal pins, and the plurality of data lines are electrically coupled to the third signal pins.

9. The display device according to claim 1 , wherein the display panel further comprises:
a plurality of first clock signal lines and a plurality of second clock signal lines disposed in the peripheral area, wherein the plurality of first output stage circuits are electrically connected to the plurality of first clock signal lines, and the plurality of second output stage circuits are electrically connected to the plurality of second clock signal lines, and the display device further comprises:
a driving chip, disposed on the substrate, and located in the peripheral area, wherein the driving chip has a plurality of first signal pins and a plurality of second signal pins, and the plurality of data lines are electrically coupled to the second signal pins; and
a flexible circuit board,
wherein the plurality of first clock signal lines and the plurality of second clock signal lines are respectively electrically coupled to the plurality of first signal pins and the flexible circuit board, or respectively electrically coupled to the flexible circuit board and the plurality of first signal pins.

10. The display device according to claim 1 , wherein the display panel further comprises:
a plurality of first clock signal lines and a plurality of second clock signal lines, disposed in the peripheral area, wherein the plurality of first outpu

Assignees

• Hannstar Display Corp

Inventors

• Chen Jing-Xuan
• Chen Yen-Chung
• Kang Mu-Kai
• Luo Qi-En
• Yeh Cheng-Yen

Classifications

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2310/0289

  Details of voltage level shifters arranged for use in a driving circuit · CPC title

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title