Adaptive block mapping

Patent metadata

Field	Value
Publication number	US-12353770-B2
Application number	US-202418586207-A
Country	US
Kind code	B2
Filing date	Feb 23, 2024
Priority date	May 20, 2022
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Methods, systems, and devices for adaptive block mapping are described. In some examples, a first superblock and a second superblock may be established across one or more dice of a memory device. The superblocks may each include one or more blocks from a plurality of planes of a memory die. In some examples, the second superblock may include at least one bad block (e.g., defective block) in addition to one or more good blocks (e.g., non-defective blocks). The memory device may receive a command for writing data in a first mode and may write a first subset of the data to the first superblock in the first mode, a second subset of the data to the second superblock in the first mode, and one or more blocks associated with the second superblock in a second mode. Additionally or alternatively, the memory device may receive a second command for writing data in the second mode and may write the data to the first superblock in the first mode.

First claim

What is claimed is:

1. An apparatus, comprising:
one or more memories comprising a plurality of planes that each comprise a plurality of blocks; and
one or more controllers coupled with the one or more memories and operable to:
write, in a first mode, a first portion of first data to a first set of blocks of the plurality of blocks and a second portion of the first data to a first subset of a second set of blocks of the plurality of blocks based at least in part on receiving one or more commands from a host device, wherein the first mode comprises writing a plurality of bits of data per memory cell; and
write, in a second mode, a third portion of the first data to a second subset of blocks of the second set of blocks based at least in part on receiving the one or more commands from the host device, wherein the second mode comprises writing one bit of data per memory cell.

2. The apparatus of claim 1 , wherein the one or more memories comprise a plurality of memory dies, and wherein each memory die of the plurality of memory dies includes at least a portion of the first subset and the second subset of blocks of the second set of blocks.

3. The apparatus of claim 1 , wherein the one or more controllers are further operable to:
maintain a first cursor to indicate a current write location for writing in the first mode, wherein writing the first portion of the first data is based at least in part on maintaining the first cursor.

4. The apparatus of claim 3 , wherein the one or more controllers are further operable to:
maintain a second cursor to indicate a location of a block having one or more defects within the second set of blocks; and
refrain from writing the third portion of the first data based at least in part on maintaining the second cursor.

5. The apparatus of claim 1 , wherein the first set of blocks comprises no blocks having one or more defects and the second set of blocks comprises at least one block having one or more defects.

6. The apparatus of claim 5 , wherein the second subset of blocks of the second set of blocks are located in a different plane than the at least one block having one or more defects.

7. The apparatus of claim 1 , wherein each block of the plurality of blocks includes a plurality of non-volatile memory cells.

8. An apparatus, comprising:
one or more memory devices; and
one or more controllers coupled with the one or more memory devices and configured to cause the apparatus to:
write a first portion of first data to a first set of blocks of a plurality of blocks based at least in part on receiving one or more first commands from a host device, wherein the first portion of the first data is written while the one or more memory devices are operating in a first mode which comprises writing a plurality of bits of data per memory cell;
receive one or more second commands from the host device to write a second portion of the first data to a portion of blocks of the plurality of blocks;
refrain from writing the second portion of the first data to a second set of blocks based at least in part on identifying that the second set of blocks contains at least one block with identified defects; and
write the second portion of the first data to a third set of blocks of the plurality of blocks based at least in part on receiving the one or more second commands from the host device, wherein the second portion of the first data is written while the one or more memory devices are operating in a second mode which comprises writing one bit of data per memory cell.

9. The apparatus of claim 8 , wherein the third set of blocks comprises a subset of the first set of blocks.

10. The apparatus of claim 8 , wherein the third set of blocks is located in a different plane than the second set of blocks.

11. The apparatus of claim 8 , wherein the first set of blocks includes a different quantity of blocks than the third set of blocks.

12. The apparatus of claim 8 , wherein the one or more first commands comprise one or more logical addresses for writing the first portion of the first data to the first set of blocks in the first mode.

13. The apparatus of claim 8 , wherein the one or more controllers are further configured to:
maintain a first cursor to indicate a current write location for writing in the first mode, wherein writing the first portion of the first data is based at least in part on maintaining the first cursor.

14. The apparatus of claim 13 , wherein the one or more controllers are further configured to:
maintain a second cursor to indicate a location of at least one block having one or more defects, wherein refraining from writing the second portion of the first data is based at least in part on maintaining the second cursor.

15. The apparatus of claim 8 , wherein the one or more memory devices comprise one or more managed memory devices.

16. An apparatus, comprising:
a memory array comprising a plurality of planes that each comprise a plurality of blocks; and
one or more controllers in electronic communication with the memory array, wherein the one or more controllers are configured to cause the apparatus to:
write a first portion of first data to a first set of blocks of the plurality of blocks based at least in part on receiving one or more first commands from a host device, wherein the first portion of the first data is written during operation of a first mode, the first mode comprising writing a plurality of bits of data per memory cell; and
write a second portion of the first data to a second set of blocks of the plurality of blocks based at least in part on receiving one or more second commands from the host device and a cursor associated with a location of at least one block with identified defects, wherein the second portion of the first data is written during operation of a second mode, the second mode comprising writing one bit of data per memory cell.

17. The apparatus of claim 16 , wherein the first mode is associated with a multi-level mode.

18. The apparatus of claim 16 , wherein the first mode includes signaling of addresses of the first set of blocks that are included in multiple planes.

19. The apparatus of claim 16 , wherein the second mode is associated with a single-level cell mode.

20. The apparatus of claim 16 , wherein the first set of blocks is in a different plane than the second set of blocks.

Assignees

• Micron Technology Inc

Inventors

• Sassara Alberto
• D'Eliseo Giuseppe
• Drissi Lalla Fatima
• Esposito Luigi
• Papa Paolo
• Del Prete Salvatore
• Luo Xiangang
• Zhu Xiaolai

Classifications

• G06F3/061

  Improving I/O performance · CPC title

• G06F3/0679 Primary

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0659 Primary

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F3/064

  Management of blocks · CPC title