Read disturb tracking based on statistical probability

Patent metadata

Field	Value
Publication number	US-12353752-B2
Application number	US-202117481786-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 22, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

An embodiment of an electronic apparatus may include one or more substrates, and a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units and, in response to a read request, increment one or more global RD counters that correspond to the read request, determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit and, if so determined, increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1. An electronic apparatus, comprising:
one or more substrates; and
a controller coupled to the one or more substrates, the controller including circuitry to control access to NAND-based storage media that includes a plurality of NAND devices, maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units, and, in response to a read request:
increment one or more global RD counters that correspond to the read request,
determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit, and, if so determined,
increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit.

2. The apparatus of claim 1 , wherein one of the two or more tracked units corresponds to a wordline (WL), and wherein the circuitry is further to:
maintain respective RD counters on a per WL per source gate select (SGS) basis.

3. The apparatus of claim 1 , wherein one of the two or more tracked units corresponds to a selected granularity that spans two or more wordlines, and wherein the circuitry is further to:
maintain respective per selected granularity RD counters.

4. The apparatus of claim 1 , wherein one of the two or more tracked units corresponds to an erase block (EB), and wherein the circuitry is further to:
maintain respective per EB RD counters.

5. The apparatus of claim 1 , wherein the circuitry is further to:
determine if one or more of the RD counters exceeds a threshold; and, if so determined,
trigger relocation of data that corresponds to the RD counter that exceeds the threshold.

6. The apparatus of claim 1 , wherein the circuitry is further to:
journal RD counter information.

7. The apparatus of claim 1 , wherein, at initialization, the circuitry is further to:
initialize all of the RD counters for each of the two or more tracked units to zero;
initialize all of the global RD counters for each of the two or more tracked units to zero; and
generate respective random numbers for each of the two or more tracked units.

8. The apparatus of claim 1 , wherein the controller and the NAND-based storage media are incorporated in a solid-state drive.

9. An electronic storage system, comprising:
NAND-based storage media that includes a plurality of NAND devices; and
a controller communicatively coupled to the NAND-based storage media, the controller including circuitry to maintain respective read disturb (RD) counters for each of two or more tracked units at respective granularities, maintain respective global RD counters for each of the two or more tracked units, and, in response to a read request:
increment one or more global RD counters that correspond to the read request,
determine if a global RD counter for a tracked unit matches a random number associated with the tracked unit, and, if so determined,
increment a RD counter for the tracked unit that corresponds to the read request and generate a new random number for the tracked unit.

10. The system of claim 9 , wherein one of the two or more tracked units corresponds to a wordline (WL), and wherein the circuitry is further to:
maintain respective RD counters on a per WL per source gate select (SGS) basis.

11. The system of claim 9 , wherein one of the two or more tracked units corresponds to a selected granularity that spans two or more wordlines, and wherein the circuitry is further to:
maintain respective per selected granularity RD counters.

12. The system of claim 9 , wherein one of the two or more tracked units corresponds to an erase block (EB), and wherein the circuitry is further to:
maintain respective per EB RD counters.

13. The system of claim 9 , wherein the circuitry is further to:
determine if one or more of the RD counters exceeds a threshold; and, if so determined,
trigger relocation of data that corresponds to the RD counter that exceeds the threshold.

14. The system of claim 9 , wherein the circuitry is further to:
journal RD counter information.

15. The system of claim 9 , wherein, at initialization, the circuitry is further to:
initialize all of the RD counters for each of the two or more tracked units to zero;
initialize all of the global RD counters for each of the two or more tracked units to zero; and
generate respective random numbers for each of the two or more tracked units.

16. The system of claim 9 , wherein the controller and the NAND-based storage media are incorporated in a solid-state drive.

17. A method of controlling storage, comprising:
controlling access to NAND-based storage media that includes a plurality of NAND devices;
maintaining respective read disturb (RD) counters for each of two or more tracked units at respective granularities;
maintaining respective global RD counters for each of the two or more tracked units, and, in response to a read request:
incrementing one or more global RD counters that correspond to the read request,
determining if a global RD counter for a tracked unit matches a random number associated with the tracked unit, and, if so determined,
incrementing a RD counter for the tracked unit that corresponds to the read request and generating a new random number for the tracked unit.

18. The method of claim 17 , wherein one of the two or more tracked units corresponds to a wordline (WL), further comprising:
maintaining respective RD counters on a per WL per source gate select (SGS) basis.

19. The method of claim 17 , wherein one of the two or more tracked units corresponds to a selected granularity that spans two or more wordlines, further comprising:
maintaining respective per selected granularity RD counters.

20. The method of claim 17 , wherein one of the two or more tracked units corresponds to an erase block (EB), further comprising:
maintaining respective per EB RD counters.

21. The method of claim 17 , further comprising:
determining if one or more of the RD counters exceeds a threshold; and, if so determined,
triggering relocation of data that corresponds to the RD counter that exceeds the threshold.

22. The method of claim 17 , further comprising:
journaling RD counter information.

23. The method of claim 17 , further comprising, at initialization:
initializing all of the RD counters for each of the two or more tracked units to zero;
initializing all of the global RD counters for each of the two or more tracked units to zero; and
generating respective random numbers for each of the two or more tracked units.

24. The method of claim 17 , wherein the NAND-based storage media is incorporated in a solid-state drive.

Assignees

• Intel Corp

Inventors

• Khan Mohammad Nasim Imtiaz
• Wakchaure Yogesh B
• Hoffman Eric
• Mielke Neal
• Bahirat Shirish
• Uhlman Cole
• Zhang Ye
• Ramalingam Anand

Classifications

• G11C16/3422

  Circuits or methods to evaluate read or write disturbance in nonvolatile memory, without steps to mitigate the problem · CPC title

• G11C16/3418

  Disturbance prevention or evaluation; Refreshing of disturbed memory data · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F2212/7203

  Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks · CPC title