Graphics security with synergistic encryption, content-based and resource management technology

Patent metadata

Field	Value
Publication number	US-12353520-B2
Application number	US-202017133367-A
Country	US
Kind code	B2
Filing date	Dec 23, 2020
Priority date	Nov 2, 2020
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

Methods, apparatuses and system provide for technology that interleaves a plurality of verification commands with a plurality of copy commands in a command buffer, wherein each copy command includes a message authentication code (MAC) derived from a master session key, wherein one or more of the plurality of verification commands corresponds to a copy command in the plurality of copy commands, and wherein a verification command at an end of the command buffer corresponds to contents of the command buffer. The technology may also add a MAC generation command to the command buffer, wherein the MAC generation command references an address of a compute result.

First claim

We claim:

1. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
partition a neural network inference model into a plurality of slices including a first slice and a second slice;
allocate different sets of resources to the plurality of slices based on one or more of a performance condition or a security condition, wherein the different sets of resources include a first set of resources and a second set of resources; and
coordinate, via a shared key, an execution of the plurality of slices by the different sets of resources by
a protection of a shared memory with the shared key;
an instruction to the first set of resources to store temporary values associated with the first slice to the shared memory; and
an instruction to the second set of resources to execute the second slice based on the temporary values to obtain an inference result.

2. The apparatus of claim 1 , wherein to coordinate the execution of the plurality of slices, the logic coupled to the one or more substrates is to:
provision the shared key to the first set of resources and the second set of resources;
notify the first set of resources and the second set of resources of one another and the shared key; and
conduct a mutual attestation between the first set of resources and the second set of resources.

3. The apparatus of claim 2 , wherein to coordinate the execution of the plurality of slices, the logic coupled to the one or more substrates is to:
instruct the first set of resources to execute the first slice based on an inference input; and
output the inference result.

4. The apparatus of claim 3 , wherein the first slice is to include a first set of neural network layers and the second slice is to include a second set of neural network layers.

5. The apparatus of claim 1 , wherein the first set of resources is to include one or more of a graphics processor compute engine, an accelerator or a smart network interface card; and
wherein the second set of resources is to include one or more host processor cores.

6. The apparatus of claim 1 , wherein the neural network inference model is to be partitioned based on one or more of the performance condition or the security condition.

7. At least one non-transitory computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
partition a neural network inference model into a plurality of slices including a first slice and a second slice;
allocate different sets of resources to the plurality of slices based on one or more of a performance condition or a security condition, wherein the different sets of resources include a first set of resources and a second set of resources; and
coordinate, via a shared key, an execution of the plurality of slices by the different sets of resources by
a protection of a shared memory with the shared key;
an instruction to the first set of resources to store temporary values associated with the first slice to the shared memory; and
an instruction to the second set of resources to execute the second slice based on the temporary values to obtain an inference result.

8. The at least one non-transitory computer readable storage medium of claim 7 , wherein to coordinate the execution of the plurality of slices, the instructions, when executed, further cause the computing system to:
provision the shared key to the first set of resources and the second set of resources;
notify the first set of resources and the second set of resources of one another and the shared key; and
conduct a mutual attestation between the first set of resources and the second set of resources.

9. The at least one non-transitory computer readable storage medium of claim 8 , wherein to coordinate the execution of the plurality of slices, the instructions, when executed, further cause the computing system to:
instruct the first set of resources to execute the first slice based on an inference input; and
output the inference result.

10. The at least one non-transitory computer readable storage medium of claim 9 , wherein the first slice is to include a first set of neural network layers and the second slice is to include a second set of neural network layers.

11. The at least one non-transitory computer readable storage medium of claim 7 ,
wherein the first set of resources is to include one or more of a graphics processor compute engine, an accelerator or a smart network interface card; and
wherein the second set of resources is to include one or more host processor cores.

12. The at least one non-transitory computer readable storage medium of claim 7 ,
wherein the neural network inference model is to be partitioned based on one or more of the performance condition or the security condition.

13. A computing system comprising:
a graphics processor; and
a memory coupled to the graphics processor, the memory including a set of instructions, which when executed by the graphics processor, cause the graphics processor to:
partition a neural network inference model into a plurality of slices including a first slice and a second slice;
allocate different sets of resources to the plurality of slices based on one or more of a performance condition or a security condition, wherein the different sets of resources include a first set of resources and a second set of resources; and
coordinate, via a shared key, an execution of the plurality of slices by the different sets of resources by
a protection of a shared memory with the shared key;
an instruction to the first set of resources to store temporary values associated with the first slice to the shared memory; and
an instruction to the second set of resources to execute the second slice based on the temporary values to obtain an inference result.

14. The computing system of claim 13 , wherein to coordinate the execution of the plurality of slices, the instructions, when executed, further cause the graphics processor to:
provision the shared key to the first set of resources and the second set of resources;
notify the first set of resources and the second set of resources of one another and the shared key; and
conduct a mutual attestation between the first set of resources and the second set of resources.

15. The computing system of claim 14 , wherein to coordinate the execution of the plurality of slices, the instructions, when executed, further cause the graphics processor to:
instruct the first set of resources to execute the first slice based on an inference input; and
output the inference result.

16. The computing system of claim 15 , wherein the first slice is to include a first set of neural network layers and the second slice is to include a second set of neural network layers.

17. The computing system of claim 13 ,
wherein the first set of resources is to include one or more of a graphics processor compute engine, an accelerator or a smart network interface card; and
wherein the second set of resources is to include one or more host processor cores.

18. The computing system of claim 13 , wherein the neural network inference model is to be partitioned based on one or more of the performance condition or the security condition.

Assignees

• Intel Corp

Inventors

• Smith Ned M
• Kumar Gaurav
• Nayshtut Alex
• Lal Reshma
• Dewan Prashant
• Pappachan Pradeep
• Poornachandran Rajesh
• Ben-Shalom Omer

Classifications

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N3/094

  Adversarial learning · CPC title

• G06N3/0475

  Generative networks · CPC title

• H04L63/061

  for key exchange, e.g. in peer-to-peer networks (cryptographic mechanisms or cryptographic arrangements for key agreement H04L9/0838) · CPC title

• H04L9/3242

  involving keyed hash functions, e.g. message authentication codes [MACs], CBC-MAC or HMAC · CPC title