Solid-state disk access control method and apparatus, computer device, and storage medium

US12353304B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12353304-B2
Application numberUS-202418982101-A
CountryUS
Kind codeB2
Filing dateDec 16, 2024
Priority dateNov 10, 2022
Publication dateJul 8, 2025
Grant dateJul 8, 2025

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

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A solid-state disk access control method and apparatus, a computer device, and a storage medium are provided. The method includes: detecting controller nodes connected to a Peripheral Component Interconnect Express (PCIe) switch and Non-Volatile Memory Express (NVMe) solid-state disks connected to the PCIe switch; setting a first mapping connection relationship to be formed between each NVMe solid-state disk and one of the controller nodes, and setting second mapping connection relationships to be formed between each NVMe solid-state disk and the remaining controller nodes; and under a condition that any NVMe solid-state disk is accessed, in response to a determination that the first mapping connection relationship is abnormal, selecting one of the remaining controller nodes as a standby controller of the accessed NVMe solid-state disk, and modifying the second mapping connection relationship between the standby controller and the accessed NVMe solid-state disk to the first mapping connection relationship.

First claim

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The invention claimed is: 1. A solid-state disk access control method, comprising: detecting all controller nodes connected to a Peripheral Component Interconnect Express (PCIe) switch and all Non-Volatile Memory Express (NVMe) solid-state disks connected to the PCIe switch, wherein each NVMe solid-state disk is connected to all the controller nodes through the PCIe switch; setting a first mapping connection relationship to be formed between each NVMe solid-state disk and one controller node of all the controller nodes, and setting second mapping connection relationships to be formed between each NVMe solid-state disk and remaining controller nodes of all the controller nodes, wherein the first mapping connection relationship is a mapping connection between the one controller node of all the controller nodes and a real capacity space of the NVMe solid-state disk, and the second mapping connection relationships are mapping connections between the remaining controller nodes and virtual spaces of the NVMe solid-state disk; and when any NVMe solid-state disk is accessed, in response to the first mapping connection relationship being normal, performing input and output read-write operation on an accessed NVMe solid-state disk through the one controller node of all the controller nodes corresponding to the first mapping connection relationship, and, in response to the first mapping connection relationship being abnormal, selecting one of the remaining controller nodes as a standby controller of the accessed NVMe solid-state disk, and modifying the second mapping connection relationship between the standby controller and the accessed NVMe solid-state disk to the first mapping connection relationship. 2. The solid-state disk access control method according to claim 1 , wherein during the detecting all controller nodes connected to a PCIe switch and all NVMe solid-state disks connected to the PCIe switch, synchronously obtaining a quantity m+1 of all the controller nodes, where m is a positive integer. 3. The solid-state disk access control method according to claim 2 , wherein the setting a first mapping connection relationship to be formed between each NVMe solid-state disk and one controller node of all the controller nodes, and setting second mapping connection relationships to be formed between each NVMe solid-state disk and remaining controller nodes of all the controller nodes comprises: for each NVMe solid-state disk, constructing one real capacity space and m virtual spaces according to the quantity m+1 of the controller nodes; and mapping the one real capacity space corresponding to each NVMe solid-state disk into the one controller node of all the controller nodes to form the first mapping connection relationship, and respectively mapping the m virtual spaces corresponding to the NVMe solid-state disk into the remaining controller nodes to form the second mapping connection relationships. 4. The solid-state disk access control method according to claim 3 , wherein the one real capacity space achieves an Input and Output (IO) read-write operation, and the m virtual spaces do not achieve the IO read-write operation. 5. The solid-state disk access control method according to claim 3 , wherein each of the m virtual spaces is a place holder. 6. The solid-state disk access control method according to claim 3 , wherein the mapping the one real capacity space corresponding to each NVMe solid-state disk into the one controller node of all the controller nodes comprises: respectively mapping, according to an arrangement sequence of all the controller nodes, the real capacity spaces in continuously arranged NVMe solid-state disks in sequence into m+1 controller nodes of all the controller nodes corresponding to each PCIe switch. 7. The solid-state disk access control method according to claim 6 , wherein m=3, and a quantity m+1 of all the controller nodes is 4. 8. The solid-state disk access control method according to claim 2 , wherein during the detecting all controller nodes connected to a PCIe switch and all NVMe solid-state disks connected to the PCIe switch, synchronously obtaining a quantity n+1 of all the NVMe solid-state disks, wherein n is greater than or equal to m, where n is a positive integer. 9. The solid-state disk access control method according to claim 8 , wherein in response to n being equal to m, according to an arrangement sequence of all the NVMe solid-state disks, n+1 real capacity spaces in n+1 continuously arranged NVMe solid-state disks of all the NVMe solid-state disks are respectively mapped into m+1 controller nodes of all the controller nodes. 10. The solid-state disk access control method according to claim 8 , wherein in response to n being greater than m, according to an arrangement sequence of all the NVMe solid-state disks, setting m+1 continuously arranged NVMe solid-state disks of all the NVMe solid-state disks as a group; wherein m+1 real capacity spaces in the group are respectively mapped into m+1 controller nodes of all the controller nodes, and real capacity spaces in a remaining group are respectively mapped into different controller nodes of all the controller nodes according to a same mapping rule. 11. The solid-state disk access control method according to claim 8 , wherein a plurality of PCIe switches are comprised, and in response to n being equal to m or n being greater than m, all the NVMe solid-state disks where the real capacity spaces in a same controller node of all the controller nodes corresponding to different PCIe switches of the plurality of PCIe switches are located are different. 12. The solid-state disk access control method according to claim 1 , wherein the modifying the second mapping connection relationship between the standby controller and the accessed NVMe solid-state disk to the first mapping connection relationship comprises: replacing a virtual space of the standby controller with a real capacity space of the accessed NVMe solid-state disk through an NVMe solid-state disk hot-access manner. 13. The solid-state disk access control method according to claim 12 , wherein in response to selecting one of the remaining controller nodes as the standby controller of the accessed NVMe solid-state disk, the method further comprises: performing one-by-one detection on whether the remaining controller nodes are normal; in response to the remaining controller nodes being normal, selecting a normal controller node as the standby controller of the accessed NVMe solid-state disk; and in response to the remaining controller nodes being abnormal, deleting an abnormal controller node, and detecting and determining again whether residual controller nodes of the remaining controller nodes are normal until at least one residual controller node is normal. 14. The solid-state disk access control method according to claim 13 , wherein during the one-by-one detection on whether the remaining controller nodes are normal, in response to the remaining controller nodes being abnormal, sending alarm information. 15. The solid-state disk access control method according to claim 1 , wherein a plurality of PCIe switches are comprised; each controller node is communicated to all the NVMe solid-state disk through each of the plurality of PCIe switches; during the detecting all controller nodes connected to a PCIe switch and all NVMe solid-state disks connected to the PCIe switch, a quantity m+1 of all the controller nodes connected to each of the plurality of PCIe switches and a quantity n+1 of all the NVMe solid-state disks connected to each of the plurality of PCIe switches are furt

Assignees

Inventors

Classifications

  • Redundant storage or storage space (G06F11/2056 takes precedence) · CPC title

  • with more than one idle spare processing component · CPC title

  • Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

  • in a memory management context, e.g. virtual memory or cache management (memory management G06F12/00; testing of static memory units G11C29/00) · CPC title

  • Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

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What does patent US12353304B2 cover?
A solid-state disk access control method and apparatus, a computer device, and a storage medium are provided. The method includes: detecting controller nodes connected to a Peripheral Component Interconnect Express (PCIe) switch and Non-Volatile Memory Express (NVMe) solid-state disks connected to the PCIe switch; setting a first mapping connection relationship to be formed between each NVMe so…
Who is the assignee on this patent?
Suzhou Metabrain Intelligent Technology Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/2094. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jul 08 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).