Serial presence detect reliability

Patent metadata

Field	Value
Publication number	US-12353283-B2
Application number	US-202418629677-A
Country	US
Kind code	B2
Filing date	Apr 8, 2024
Priority date	Jul 15, 2021
Publication date	Jul 8, 2025
Grant date	Jul 8, 2025

Abstract

A serial presence detect (SPD) device includes nonvolatile memory to store SPD information. Parity information suitable for single error correct and double error detect (SEC-DED) is also stored in association with the SPD information in the nonvolatile memory. The combination of SPD information and parity information is organized into codewords addressable at each memory location. During an initialization period occurring after a power on reset and before the SPD device is accepting I2C commands, the SPD device checks each memory location (codeword) for errors. Each error detected is counted to provide an indicator of device health. Before the initialization period expires, the SPD device writes a corrected codeword back to the nonvolatile memory.

First claim

What is claimed is:

1. A serial presence detect memory device, comprising:
a first plurality of nonvolatile memory cells organized into memory locations that each access a plurality of data bits;
a second plurality of nonvolatile memory cells organized into corresponding memory locations that each access a plurality of error detection and correction information bits, the plurality of data bits at each memory location and the plurality of error detection and correction information bits at each corresponding memory location forming codewords accessed at each memory location; and
error detection circuitry to access the codewords at each memory location and to detect and correct an error in a first codeword to form a corrected first codeword and to write the corrected first codeword to a first memory location where the first codeword was read from.

2. The serial presence detect memory device of claim 1 , wherein the error detection circuitry is to access the codewords at each memory location during an initialization period.

3. The serial presence detect memory device of claim 1 , wherein the first codeword is a one of a plurality of codewords stored by the serial presence detect memory device having errors.

4. The serial presence detect memory device of claim 1 , further comprising:
counting circuitry to count a number of errors detected.

5. The serial presence detect memory device of claim 4 , wherein the counting circuitry counts the number of errors detected during an initialization period.

6. The serial presence detect memory device of claim 4 , wherein the counting circuitry counts the number of errors detected after an initialization period.

7. The serial presence detect memory device of claim 4 , wherein the counting circuitry counts the number of errors detected during an initialization period and after the initialization period.

8. A memory module, comprising:
a plurality of volatile memory devices;
a nonvolatile memory device comprising:
first nonvolatile memory circuitry to store serial presence detect data;
second nonvolatile memory circuitry to store error detect and correct (EDC) data computed from the serial presence detect data; and
scanning circuitry to read contents of the first nonvolatile memory circuitry and the second nonvolatile memory circuitry and to, in response to detecting an error in a first entry stored by the nonvolatile memory device in either the first nonvolatile memory circuitry and the second nonvolatile memory circuitry, correct the first entry and write a corrected first entry to the first nonvolatile memory circuitry and the second nonvolatile memory circuitry.

9. The memory module of claim 8 , wherein the scanning circuitry of the nonvolatile memory device reads all the first nonvolatile memory circuitry and the second nonvolatile memory circuitry.

10. The memory module of claim 8 , wherein the scanning circuitry of the nonvolatile memory device reads all the first nonvolatile memory circuitry and the second nonvolatile memory circuitry during an initialization period.

11. The memory module of claim 8 , wherein the first entry stored by the nonvolatile memory device is a one of a plurality of entries stored by the nonvolatile memory device with errors.

12. The memory module of claim 8 , wherein the nonvolatile memory device further comprises:
counting circuitry to count a number of errors detected.

13. The memory module of claim 12 , wherein the counting circuitry of the nonvolatile memory device counts the number of errors detected during an initialization period.

14. The memory module of claim 12 , wherein the counting circuitry of the nonvolatile memory device counts the number of errors detected after an initialization period.

15. A method, comprising:
storing codewords having data information and error correcting information in a plurality of nonvolatile memory locations;
determining whether each of the codewords has an error;
detecting a first error in a first codeword read from a first nonvolatile memory location;
based on detecting the first error, advancing an error count;
correcting the first error in the first codeword to generate a corrected first codeword; and
storing the corrected first codeword to the first nonvolatile memory location.

16. The method of claim 15 , further comprising:
detecting a second error in a second codeword read from a second nonvolatile memory location.

17. The method of claim 16 , further comprising:
based on detecting the second error in the second codeword, advancing the error count.

18. The method of claim 16 , further comprising:
based on detecting the second error in the second codeword, correcting the second error in the second codeword to generate a corrected second codeword; and
based on detecting the second error in the second codeword, storing the corrected second codeword to the second nonvolatile memory location.

19. The method of claim 15 , further comprising:
iteratively reading the codewords from the plurality of nonvolatile memory locations.

20. The method of claim 19 , wherein iteratively reading the codewords from the plurality of nonvolatile memory locations and advancing the error count occur during an initialization period.

Assignees

• Rambus Inc

Inventors

• Shallal Aws
• Chen Chen

Classifications

• G06F11/076

  by exceeding a count or rate limit, e.g. word- or bit count limit · CPC title

• G06F11/1658

  Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit · CPC title

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title