Display panel, method for manufacturing same, and display device

Patent metadata

Field	Value
Publication number	US-12349565-B2
Application number	US-202117637340-A
Country	US
Kind code	B2
Filing date	Feb 24, 2021
Priority date	Feb 7, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Provided is a display panel, including: a base substrate provided with a first display region and a second display region; a first auxiliary electrode layer, a first anode layer, a first light-emitting layer and a first cathode layer that are sequentially laminated, in a direction away from the base substrate, in the first display region; and a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer that are sequentially laminated, in the direction away from the base substrate, in the second display region; wherein the first auxiliary electrode layer is connected to the first cathode layer and the second auxiliary electrode layer, and the second cathode layer is connected to the first cathode layer, the second cathode layer is provided with at least one hollowed-out region.

First claim

What is claimed is:

1. A display panel, comprising:
a base substrate provided with a first display region and a second display region;
a first auxiliary electrode layer, a first anode layer, a first light-emitting layer and a first cathode layer that are sequentially laminated, in a direction away from the base substrate, in the first display region; and
a second auxiliary electrode layer, a second anode layer, a second light-emitting layer, and a second cathode layer that are sequentially laminated, in the direction away from the base substrate, in the second display region;
wherein the first auxiliary electrode layer is connected to the first cathode layer and the second auxiliary electrode layer, and the second cathode layer is connected to the first cathode layer, the second cathode layer is provided with at least one hollowed-out region;
the display panel further comprising a plurality of pixel circuits disposed in the second display region, and each of the pixel circuits comprising at least one layer of opaque patterns; wherein the second auxiliary electrode layer comprises a plurality of auxiliary electrode patterns electrically connected; and at least 50% of areas of orthographic projections of the at least one layer of opaque patterns in at least one of the pixel circuits onto the base substrate is overlapped with orthographic projections of the auxiliary electrode patterns onto the base substrate.

2. The display panel according to claim 1 , wherein the orthographic projections of the auxiliary electrode patterns onto the base substrate cover the orthographic projections of the at least one layer of opaque patterns in at least one of the pixel circuits onto the base substrate.

3. The display panel according to claim 1 , wherein edges of the orthographic projection of the auxiliary electrode pattern onto the base substrate are at least partially arc-shaped.

4. The display panel according to claim 1 , wherein the auxiliary electrode pattern comprises a first pattern and a second pattern;
an orthographic projection of the first pattern onto the base substrate is overlapped with 50% or more of the areas of the orthographic projections of the at least one layer of opaque patterns in at least one of the pixel circuits onto the base substrate; and
the second pattern is configured to be electrically connected to the auxiliary electrode patterns adjacent to the second pattern.

5. The display panel according to claim 4 , wherein the orthographic projection of the first pattern onto the base substrate is circular.

6. The display panel according to claim 1 , wherein the base substrate is further provided with a peripheral region surrounding both the first display region and the second display region; and
the first auxiliary electrode layer and the first cathode layer are further disposed in the peripheral region, and a portion disposed in the peripheral region of the first auxiliary electrode layer is electrically connected to a portion disposed in the peripheral region of the first cathode layer.

7. The display panel according to claim 6 , wherein an orthographic projection of the first auxiliary electrode layer onto the base substrate covers the first display region;
the peripheral region comprises a first region and a second region that are arranged oppositely and in parallel, as well as a third region and a fourth region that are arranged oppositely and in parallel, a direction in which the first region extends is perpendicular to a direction in which the third region extends, and a distance between the second display region and the first region is less than a distance between the second display region and the second region;
wherein a portion disposed in the first region of the first auxiliary electrode layer is connected to a portion disposed in the first region of the first cathode layer, a portion disposed in the third region of the first auxiliary electrode layer is connected to a portion disposed in the third region of the first cathode layer, and a portion disposed in the fourth region of the first auxiliary electrode layer is connected to a portion disposed in the fourth region of the first cathode layer; and
a portion disposed in the second region of the first auxiliary electrode layer is not connected to a portion disposed in the second region of the first cathode layer.

8. The display panel according to claim 1 , wherein the plurality of auxiliary electrode patterns are overlapped with each other.

9. The display panel according to claim 1 , further comprising a plurality of first connection electrodes disposed in the second display region, wherein the plurality of auxiliary electrode patterns are electrically connected by the plurality of first connection electrodes.

10. The display panel according to claim 1 , further comprising an active layer, a buffer layer, a first gate insulation layer, a first gate layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer and a first source/drain layer that are sequentially laminated, in the direction away from the base substrate, in both the first display region and the second display region;
the first source/drain layer comprises a plurality of sets of first source/drain layer patterns corresponding to the pixel circuits, the active layer comprises a plurality of sets of active patterns corresponding to the pixel circuits, the first gate layer comprises a plurality of sets of first gate layer patterns corresponding to the pixel circuits, and the second gate layer comprises a plurality of sets of second gate layer patterns corresponding to the pixel circuits; and
the at least one layer of opaque patterns of the pixel circuit comprise one set of the first source/drain layer patterns disposed in the first source/drain layer, one set of the active patterns disposed in the active layer, one set of the first gate patterns disposed in the first gate layer, and one set of the second gate patterns disposed in the second gate layer.

11. The display panel according claim 10 , further comprising a first conduction layer disposed in a same layer as the first source/drain layer, and a second conduction layer disposed in a same layer as the second gate layer, wherein the buffer layer, the first gate insulation layer, the second gate insulation layer and the interlayer dielectric layer are all provided with a first via hole, the second conduction layer and the first conduction layer being electrically connected to the auxiliary electrode patterns through the first via holes; and
further comprising a passivation layer and a first planarization layer that are disposed on a side, distal from the base substrate, of the first source/drain layer, as well as a plurality of first connection electrodes disposed between the passivation layer and the first planarization layer;
wherein the passivation layer is provided with a second via hole, at least part of the first connection electrodes is disposed in the second via hole and connected to the first conduction layer, and the plurality of first connection electrodes are configured to connect the plurality of auxiliary electrode patterns.

12. The display panel according to claim 10 , further comprising a passivation layer and a first planarization layer that are disposed on a side, distal from the base substrate, of the first source/drain layer, a plurality of second connection electrodes disposed between the passivation layer and the first planarization layer, a first signal transmission layer disposed in a same layer as the first source/drain layer, and a third conduction layer disposed in a same layer as the first gate layer;
the first gate insulation layer, th

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Liu Changchang
• Shi Ling
• Liu Ke
• Chen Yipeng
• Zhang Zhenhua
• Lu Hui

Classifications

• H10K59/65

  OLEDs integrated with inorganic image sensors · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• H10K59/80516

  combined with auxiliary electrodes, e.g. ITO layer combined with metal lines · CPC title

• H10K59/80522

  combined with auxiliary electrodes · CPC title

• H10K59/80521 Primary

  characterised by their shape · CPC title