Method for making active area air gap

Patent metadata

Field	Value
Publication number	US-12349343-B2
Application number	US-202318152868-A
Country	US
Kind code	B2
Filing date	Jan 11, 2023
Priority date	May 30, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

The present application discloses a method for making an active area air gap, comprising: step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein each word line structure spans each field oxide and each active area; step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner; step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap; and step 4, removing the protective spacer.

First claim

What is claimed is:

1. A method for making an active area air gap, comprising the following steps:
step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein a plurality of field oxides are formed on the semiconductor substrate, a plurality of active areas are isolated from each other by the field oxides, and each of the word line structures spans each of the field oxides and each of the active areas;
step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner, wherein the materials of the protective spacer and the field oxide have different etching rates;
step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap, during the isotropic etching, an etching rate of the protective spacer is less than an etching rate of the field oxide, and after the isotropic etching is completed, the protective spacer is retained on the side surface of the word line structure to protect the word line structure; and
step 4, removing the protective spacer.

2. The method for making an active area air gap according to claim 1 , before the formation of the protective spacer in step 2, further comprising performing first etching on the field oxide outside the coverage area of the word line structure, wherein the first etching is anisotropic etching, the first etching makes the top surface of the field oxide outside the coverage area of the word line structure lower than the top surface of the active area, the top surface of the field oxide within the coverage area of the word line structure is higher than the top surface of the field oxide outside the coverage area of the word line structure, and therefore the side surface of the field oxide is formed at the bottom of the word line structure; and
in step 2, within an area of the field oxide, the protective spacer extends to the side surface of the field oxide at the bottom of the word line structure.

3. The method for making an active area air gap according to claim 2 , wherein the first etching is directly implemented by means of the word line etching.

4. The method for making an active area air gap according to claim 1 , wherein an area of the word line structure that covers the top of the active area forms a gate structure of a device cell, and the gate structures of all the device cells on the same word line structure are connected together to form a row structure.

5. The method for making an active area air gap according to claim 4 , wherein all the device cells on the same active area form a column structure, and the row structure and the column structure form an array structure.

6. The method for making an active area air gap according to claim 5 , wherein in a formation area of the array structure, the length directions of all the active areas are parallel to each other.

7. The method for making an active area air gap according to claim 6 , wherein the length direction of each of the word line structures is perpendicular to the length direction of the active area.

8. The method for making an active area air gap according to claim 5 , wherein the device cell comprises a memory cell of a NAND flash, and the array structure forms a storage array of the NAND flash.

9. The method for making an active area air gap according to claim 8 , wherein a gate structure of the memory cell comprises a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer, and a control gate that are stacked in sequence.

10. The method for making an active area air gap according to claim 9 , wherein a structure of the word line structure that covers the top of the field oxide comprises the inter-gate dielectric layer and the control gate stacked in sequence; and
the tunneling dielectric layer and the floating gate are located in an overlap area of the control gate and the active area.

11. The method for making an active area air gap according to claim 3 , wherein an etching amount of the first etching on the field oxide is 200-500 Å.

12. The method for making an active area air gap according to claim 11 , wherein the material of the protective spacer is a polymer.

13. The method for making an active area air gap according to claim 12 , wherein after gate etching is completed, the polymer is directly deposited in an etching machine for the gate etching; and
after deposition of the polymer is completed, self-aligned etching is directly performed in the etching machine for the gate etching to form the protective spacer.

14. The method for making an active area air gap according to claim 13 , wherein a deposition thickness of the polymer is 10-30 Å.

15. The method for making an active area air gap according to claim 1 , wherein in step 3, an etching amount of the isotropic etching on the field oxide is ½ of the width of the word line structure.

16. The method for making an active area air gap according to claim 12 , wherein in step 4, the protective spacer is removed by means of wet etching.

Assignees

• Shanghai Huali Microelect Corp

Inventors

• Yao Shaokang
• Wang Qiwei
• Chen Haoyu

Classifications

• H10W10/20

  Air gaps · CPC title

• H10W10/021

  of air gaps · CPC title

• H10B41/10

  characterised by the top-view layout · CPC title

• H10D64/035

  comprising conductor-insulator-conductor-insulator-semiconductor structures · CPC title

• H10B41/30 Primary

  characterised by the memory core region · CPC title