Synchronous rectification to improve efficiency of electricity conversion for harvesting energy from low voltage sources

US12348149B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12348149-B2
Application numberUS-202118010745-A
CountryUS
Kind codeB2
Filing dateJun 16, 2021
Priority dateJun 16, 2020
Publication dateJul 1, 2025
Grant dateJul 1, 2025

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A DC-DC converter for converting a low voltage DC input to a higher voltage DC output, the DC-DC converter comprising: an oscillator comprising a first relatively voltage sensitive and relatively low power transistor and a second relatively voltage insensitive and relatively high power transistor, the oscillator producing an AC signal from the low voltage DC input; a first transformer for converting the AC signal produced by the oscillator to a higher voltage AC signal; an autonomous, synchronous voltage-doubling rectification circuit for converting the higher voltage AC signal to the higher voltage DC output, wherein the autonomous, synchronous voltage-doubling rectification circuit comprises a second transformer, a first shunt switch and a second shunt switch; and wherein current through the second transformer controls the synchronous rectification.

First claim

Opening claim text (preview).

The invention claimed is: 1. A DC-DC converter for converting a low voltage DC input to a higher voltage DC output, the DC-DC converter comprising: an oscillator comprising a first relatively voltage sensitive and relatively low power transistor and a second relatively voltage insensitive and relatively high power transistor, the oscillator producing an AC signal from the low voltage DC input; a first transformer for converting the AC signal produced by the oscillator to a higher voltage AC signal; an autonomous, synchronous voltage-doubling rectification circuit for converting the higher voltage AC signal to the higher voltage DC output, the autonomous, synchronous voltage-doubling rectification circuit comprising a second transformer, a first shunt switch and a second shunt switch; wherein current through the second transformer controls the autonomous, synchronous voltage-doubling rectification circuit; and wherein the second transformer comprises at least two transformers with windings, wherein the at least two transformers are coupled together in at least one of a series configuration and a parallel configuration, wherein at least one of the windings of each of the at least two transformers is coupled to a gate of the first relatively voltage sensitive and relatively low power transistor. 2. The DC-DC converter of claim 1 , wherein the first relatively voltage sensitive and relatively low power transistor is a JFET device and the second relatively voltage insensitive and relatively high power transistor is a MOSFET device. 3. The DC-DC converter of claim 1 , wherein the second relatively voltage insensitive and relatively high power transistor has a relatively lower on-resistance RDS(on) than the first relatively voltage sensitive and relatively low power transistor. 4. The DC-DC converter of claim 1 , further comprising an adaptive clamping mechanism that ensures a suitable bias for the first relatively voltage sensitive and relatively low power transistor under practical source and load conditions. 5. The DC-DC converter of claim 4 , wherein the adaptive clamping mechanism comprises a capacitor connected between an output of a secondary side of the first transformers and a gate of the first relatively voltage sensitive and relatively low power transistor, and a gate-source PN junction of the first relatively voltage sensitive and relatively low power transistor. 6. The DC-DC converter of claim 5 , wherein the autonomous, synchronous voltage-doubling rectification circuit has a first stage formed of the capacitor of the adaptive clamping mechanism and a gate-source junction of the first relatively voltage sensitive and relatively low power transistor, and a second stage formed of a diode and another capacitor. 7. The DC-DC converter of claim 6 , wherein the diode is connected between the capacitor of the adaptive clamping mechanism and the another capacitor, the diode connected to permit current flow in a direction from the another capacitor to the capacitor of the adaptive clamping mechanism. 8. The DC-DC converter of claim 7 , wherein the output isolation switch comprises at least one third transistor for isolating a load from a remainder of the DC-DC converter when there are harsh load conditions causing output terminals of the DC-DC converter to be either shorted or driven, and a resistor for allowing a leakage current following removal of the harsh load conditions such that the first relatively voltage sensitive and relatively low power transistor can start up. 9. The DC-DC converter of claim 1 , wherein a turns-ratio of at least one of the first transformer and the second transformer is selected for a particular source and load combination. 10. The DC-DC converter of claim 1 , wherein the autonomous, synchronous voltage-doubling rectification circuit has a first stage formed of a first capacitor and a gate-source junction of the first relatively voltage sensitive and relatively low power transistor, and a second stage formed of a diode and a second capacitor. 11. The DC-DC converter of claim 1 , wherein the first shunt switch and the second shunt switch are MOSFET devices. 12. The DC-DC converter of claim 1 , wherein the diode is connected between a first capacitor and a second capacitor, the diode connected to permit current flow in a direction from the second capacitor towards the first capacitor. 13. The DC-DC converter of claim 1 , further comprising an output isolation switch. 14. A power supply comprising: a low voltage source; the DC-DC converter of claim 1 . 15. A method of converting a low voltage DC input to a higher voltage DC output, the method comprising: producing an AC signal from the low voltage DC input using an oscillator comprising a first relatively voltage sensitive and relatively low power transistor and a second relatively voltage insensitive and relatively high power transistor, by starting up oscillation of the oscillator when the low voltage DC input is sufficiently high to start the oscillator initially using only the first relatively voltage sensitive and relatively low power transistor, and turning on the second relatively voltage insensitive and relatively high power transistor when the voltage on a secondary side of a first transformer exceeds the turn-on voltage of the second relatively voltage insensitive and relatively high power transistor; converting the AC signal produced by the oscillator to a higher voltage AC signal with the first transformer; rectifying the higher voltage AC signal to produce the higher voltage DC output using at least a second transformer, a first shunt switch and a second shunt switch forming a rectifier; and using an input current to the rectifier to control the timing of the first shunt switch and the second shunt switch to maximize efficiency, wherein the second transformer comprises at least two transformers with windings, wherein the at least two transformers are coupled together in at least one of a series configuration and a parallel configuration, wherein at least one of the windings of each of the at least two transformers is coupled to a gate of the first relatively voltage sensitive and relatively low power transistor. 16. The method of claim 15 , further comprising performing adaptive clamping to ensure a suitable bias for the first transistor under practical source and load conditions. 17. A DC-DC converter for converting a low voltage DC input to a higher voltage DC output, the DC-DC converter comprising: an oscillator comprising a first relatively voltage sensitive and relatively low power transistor and a second relatively voltage insensitive and relatively high-power transistor, the oscillator producing an AC signal from the low voltage DC input; a first transformer for converting the AC signal produced by the oscillator to a higher voltage AC signal; an autonomous, synchronous voltage-doubling rectification circuit for converting the higher voltage AC signal to the higher voltage DC output, wherein the autonomous, synchronous voltage-doubling rectification circuit comprises a second transformer comprising at least two transformers with windings, wherein the at least two transformers are coupled together in at least one of a series configuration and a parallel configuration, wherein at least one of the windings of each of the at least two transformers is coupled to a gate of the first relatively voltage sensitive and relatively low power transistor, a first shunt switch and a second shunt switch; and wherein the first and second transistors of the oscillator are such that the oscillator is initiall

Assignees

Inventors

Classifications

  • Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

  • Passive dissipative snubbers · CPC title

  • Means for starting or stopping converters · CPC title

  • Circuits or arrangements for reducing losses (using snubbers H02M1/34) · CPC title

  • for the simultaneous control of series or parallel connected semiconductor devices · CPC title

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What does patent US12348149B2 cover?
A DC-DC converter for converting a low voltage DC input to a higher voltage DC output, the DC-DC converter comprising: an oscillator comprising a first relatively voltage sensitive and relatively low power transistor and a second relatively voltage insensitive and relatively high power transistor, the oscillator producing an AC signal from the low voltage DC input; a first transformer for conve…
Who is the assignee on this patent?
Nat Res Council Canada
What technology area does this patent fall under?
Primary CPC classification H02M3/33592. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jul 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).