Startup detection for parallel power converters

Patent metadata

Field	Value
Publication number	US-12348134-B2
Application number	US-202318543943-A
Country	US
Kind code	B2
Filing date	Dec 18, 2023
Priority date	Mar 3, 2020
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Circuits/methods for controlling the startup of multiple parallel power converters that avoid inrush current or switch overstress in an added power converter or a power converter having fault conditions. Embodiments include node status detectors coupled to nodes within parallel-connected power converters to monitor voltage/current and configured in some embodiments to work in parallel with an output status detector measuring the startup output voltage of a power converter. With charge pump-based power converters, the node status detectors ensure that the power converter pump capacitors are charged while the output capacitor is charged as well. For such embodiments, a soft-start period of startup may be considered finished if both the shared output capacitors and the power converter pump capacitors are charged to target values. Embodiments may also be used for fault detection during steady-state operation.

First claim

What is claimed is:

1. A circuit including:
(a) a plurality of parallel power converters having direct-connected outputs;
(b) at least one node status detector coupled to at least one pump capacitor node of a corresponding one of the plurality of power converters and configured to assert a corresponding node flag signal if the at least one pump capacitor node is adequately charged to a selected level;
(c) at least one output status detector coupled to an output capacitor of a corresponding one of the plurality of power converters and configured to assert an output flag signal if the output capacitor is adequately charged to a selected level; and
(d) at least one status validation circuit coupled to at least one of the plurality of power converters, at least one of the output status detectors, and at least one of the node status detectors, the at least one status validation circuit configured (1) to receive the output flag signal and the corresponding node flag signal or signals from the coupled power converters and from the coupled status detectors and (2) provide a logic signal to at least one coupled power converter if all of the received flag signals have been asserted;
wherein the at least one coupled power converter is configured to transition to a steady-state mode of operation in response to receipt of at least the logic signal from the at least one status validation circuit and is prevented from transitioning to the steady-state mode of operation in the absence of receipt of the logic signal from the at least one status validation circuit.

2. The circuit of claim 1 , wherein at least one of the plurality of power converters includes a switched-capacitor power converter.

3. The circuit of claim 2 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

4. The circuit of claim 1 , wherein at least one of the plurality of power converters includes a symmetric cascade multiplier charge pump.

5. The circuit of claim 4 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

6. The circuit of claim 1 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

7. A plurality of parallel switched-capacitor power converter circuits having direct-connected outputs, each switched-capacitor power converter circuit configured to be coupled to one or more capacitors and including:
(a) at least one node status detector each coupled to a corresponding node of the switched-capacitor power converter circuit and configured to assert a corresponding node flag signal if the voltage and/or current at the corresponding node is sufficient to allow startup of the switched-capacitor power converter circuit to transition to a steady-state mode of operation; and
(b) a status validation circuit configured to receive the node flag signal from the at least one node status detector and prevent the plurality of parallel switched-capacitor power converter circuits from transitioning to the steady-state mode of operation unless all of the plurality of parallel switched-capacitor power converter circuits are ready to transition to the steady-state mode of operation based on the corresponding node flag signal from each of such plurality of parallel switched-capacitor power converter circuits.

8. The plurality of parallel switched-capacitor power converter circuits of claim 7 , wherein each switched-capacitor power converter circuit includes a plurality of switches coupled in series, and at least one of the plurality of switches is coupled to an associated node status detector.

9. The plurality of parallel switched-capacitor power converter circuits of claim 8 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

10. The plurality of parallel switched-capacitor power converter circuits of claim 7 , wherein at least one node is the output of the corresponding switched-capacitor power converter circuit and the at least one node status detector is coupled to the corresponding output of the switched-capacitor power converter circuit.

11. The plurality of parallel switched-capacitor power converter circuits of claim 10 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

12. The plurality of parallel switched-capacitor power converter circuits of claim 7 , wherein at least one node status detector is coupled to an output capacitor of a corresponding one of the plurality of parallel switched-capacitor power converter circuits and is configured to assert an output flag signal if the output capacitor is adequately charged to a selected level.

13. The plurality of parallel switched-capacitor power converter circuits of claim 12 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

14. The plurality of parallel switched-capacitor power converter circuits of claim 7 , wherein the at least one node status detector includes:
(a) a voltage divider network configured to receive input voltages from a symmetric pair of pump capacitor nodes and output a scaled sum of the input voltages; and
(b) a comparison circuit, coupled to the output of the voltage divider network and to a reference voltage, configured to assert the corresponding node flag signal if the voltages of the symmetric pair of pump capacitor nodes have selected values.

Assignees

• Murata Manufacturing Co

Inventors

• Aboueldahab Walid Fouad Mohamed
• Low Aichen

Classifications

• H02M3/077

  with parallel connected charge pump stages · CPC title

• H02M3/1584

  with a plurality of power processing stages connected in parallel · CPC title

• H02M3/072

  adapted to generate an output voltage whose value is lower than the input voltage · CPC title

• G01R31/40

  Testing power supplies (testing photovoltaic devices H02S50/10) · CPC title

• H02M1/325

  with means for allowing continuous operation despite a fault, i.e. fault tolerant converters · CPC title