Micro device transferring method, and micro device substrate manufactured by micro device transferring method
US-10770426-B2 · Sep 8, 2020 · US
Method of mounting electronic component
US12347806B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12347806-B2 |
| Application number | US-202217706612-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 29, 2022 |
| Priority date | Apr 2, 2021 |
| Publication date | Jul 1, 2025 |
| Grant date | Jul 1, 2025 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
According to one embodiment, a method of mounting electronic components, includes placing a workpiece comprising an insulating substrate including a first surface, a circuit board including a terminal portion and a spacer, a sapphire substrate including a second surface and a wafer including the electronic components, bringing the pressure jig into contact with a part of the sapphire substrate to apply a load on a contact part between a part of an upper surface of the spacer and the second surface, pressing the sapphire substrate toward the circuit board with the pressure jig, to bring other part of the upper surface of the spacer into contact with the second surface and flatten the sapphire substrate.
First claim
Opening claim text (preview).
What is claimed is: 1. A method of mounting electronic components, comprising: placing a workpiece comprising an insulating substrate including a first surface, a circuit board including a terminal portion located on a side of the first surface and a spacer, a sapphire substrate including a second surface and a wafer including the electronic components located on a side of the second surface, between a stage and a pressure jig so that the first surface and the second surface oppose each other; bringing the pressure jig into contact with a part of the sapphire substrate to apply a load on a contact part between a part of an upper surface of the spacer and the second surface; pressing the sapphire substrate toward the circuit board with the pressure jig to bring other part of the upper surface of the spacer into contact with the second surface and flatten the sapphire substrate; irradiating first laser beam onto the workpiece through a window of the pressure jig, and joining the electronic components to the circuit board; irradiating second laser light having a wavelength band different from that of the first laser light onto the workpiece through the window, to remove the electronic components from the sapphire substrate; and releasing the pressure jig from the sapphire substrate. 2. The method of claim 1 , wherein when the pressure jig is brought into contact with the part of the sapphire substrate to apply a load to the contact part between the part of the upper surface of the spacer and the second surface, the other part of the upper surface of the spacer is separated from the second surface. 3. The method of claim 1 , wherein when the sapphire substrate is flattened, the entire upper surface of the spacer and the second surface are in contact with each other. 4. The method of claim 1 , wherein the spacer includes a plurality of hole portions, and when the sapphire substrate is pressurized with the pressure jig toward the circuit board, the electronic components are placed in the hole portions. 5. The method of claim 1 , wherein a rigidity of the spacer is equal to or higher than a rigidity of the sapphire substrate.
Assignees
Inventors
Classifications
- H10W90/00Primary
Package configurations · CPC title
of bump connectors · CPC title
- H10W72/0198Primary
batch processes · CPC title
Apparatus therefor · CPC title
Manufacture or treatment · CPC title
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Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US12347806B2 cover?
- According to one embodiment, a method of mounting electronic components, includes placing a workpiece comprising an insulating substrate including a first surface, a circuit board including a terminal portion and a spacer, a sapphire substrate including a second surface and a wafer including the electronic components, bringing the pressure jig into contact with a part of the sapphire substrate …
- Who is the assignee on this patent?
- Japan Display Inc
- What technology area does this patent fall under?
- Primary CPC classification H10W90/00. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Jul 01 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).