Memory system

Patent metadata

Field	Value
Publication number	US-12347518-B2
Application number	US-202218068914-A
Country	US
Kind code	B2
Filing date	Dec 20, 2022
Priority date	Jul 1, 2022
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.

First claim

What is claimed is:

1. A memory system comprising:
a semiconductor memory including at least one memory cell configured to nonvolatilely store data having at least two bits;
a controller configured to cause the semiconductor memory to execute:
a first write operation of writing a first bit into the memory cell; and
a second write operation of writing first data into the memory cell, the first data having at least two bits based on the first bit read from the memory cell and a second bit; and

a first circuit configured to check whether or not the first bit read from the memory cell includes a bit error,
wherein the controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data that includes the second bit and a third bit, the third bit being obtained by correcting the bit error of the first bit, in a case that the first bit read from the memory cell includes the bit error based on a result of checking by the first circuit.

2. The memory system according to claim 1 , wherein the controller is further configured to determine whether to execute the checking by the first circuit, in executing the second write operation on the memory cell on which the first write operation has been executed.

3. The memory system according to claim 2 , wherein the controller is configured to determine whether to execute the checking by the first circuit, based on an elapsed time period from execution of the first write operation.

4. The memory system according to claim 1 , wherein the memory cell is configured to nonvolatilely store the data in accordance with a threshold voltage,
the first bit corresponds to a first threshold voltage, and
the first data, which includes the second bit and the third bit, corresponds to a second threshold voltage higher than the first threshold voltage.

5. The memory system according to claim 3 , wherein the controller is configured to determine to execute the checking by the first circuit, in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

6. The memory system according to claim 1 , wherein
the controller is connected to the semiconductor memory via a bus and includes the first circuit, and
the controller is further configured to:
determine whether to receive the first bit read from the memory cell, in executing the second write operation on the memory cell on which the first write operation has been executed; and
in a case where the controller receives the first bit read from the memory cell, check, by using the first circuit, whether or not the first bit read from the memory cell includes the bit error.

7. The memory system according to claim 6 , wherein the controller is configured to determine whether to receive the first bit read from the memory cell, based on an elapsed time period from execution of the first write operation.

8. The memory system according to claim 7 , wherein the controller is configured to determine to receive the first bit read from the memory cell, in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

9. A method of controlling a semiconductor memory that includes at least one memory cell configured to nonvolatilely store data having at least two bits, comprising:
causing the semiconductor memory to execute a first write operation of writing a first bit into the memory cell;
causing the semiconductor memory to execute a second write operation of writing first data into the memory cell, the first data having at least two bits based on the first bit read from the memory cell and a second bit; and
checking whether or not the first bit read from the memory cell includes a bit error,
wherein the semiconductor memory is caused to execute, in the second write operation, writing of the first data that includes the second bit and a third bit, the third bit being obtained by correcting the bit error of the first bit, in a case that the first bit read from the memory cell includes the bit error.

10. The method according to claim 9 , further comprising:
determining whether to execute the checking of the error bit, in executing the second write operation on the memory cell on which the first write operation has been executed.

11. The method according to claim 10 , wherein whether to execute the checking of the error bit is determined based on an elapsed time period from execution of the first write operation.

12. The method according to claim 11 , wherein the checking of the error bit is determined to be executed in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

13. The method according to claim 9 , wherein
the method is executed by a controller that is connected to the semiconductor memory via a bus and includes a first circuit, and
the method further comprises:
determining whether to receive the first bit read from the memory cell, in executing the second write operation on the memory cell on which the first write operation has been executed; and
in a case where the first bit read from the memory cell is received, checking, by using the first circuit, whether or not the first bit read from the memory cell includes the bit error.

14. The method according to claim 13 , wherein whether to receive the first bit read from the memory cell is determined based on an elapsed time period from execution of the first write operation.

15. The method according to claim 14 , wherein the first bit read from the memory cell is determined to be received in a case where the elapsed time period from the execution of the first write operation is longer than a threshold.

16. The method according to claim 9 , wherein the memory cell is configured to nonvolatilely store the data in accordance with a threshold voltage,
the first bit corresponds to a first threshold voltage, and
the first data, which includes the second bit and the third bit, corresponds to a second threshold voltage higher than the first threshold voltage.

17. The memory system according to claim 2 , wherein the controller is configured to determine whether to execute the checking by the first circuit, based on a number of data write operations performed on the memory cell or a number of data erase operations performed on the memory cell.

18. The memory system according to claim 2 , wherein the controller is configured to determine whether to execute the checking by the first circuit, based on a number of past error detections of the memory cell.

19. The method according to claim 10 , wherein whether to execute the checking of the error bit is determined based on a number of data write operations performed on the memory cell or a number of data erase operations performed on the memory cell.

20. The method according to claim 10 , wherein whether to execute the checking of the error bit is determined based on a number of past error detections of the memory cell.

Assignees

• Kioxia Corp

Inventors

• Asami Shohei
• Kojima Yoshihisa

Classifications

• G11C7/1069

  I/O lines read out arrangements · CPC title

• G11C29/52 Primary

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G06F11/1044

  with specific ECC/EDC distribution · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title