Display panel and display device

Patent metadata

Field	Value
Publication number	US-12347373-B2
Application number	US-202318290794-A
Country	US
Kind code	B2
Filing date	Mar 28, 2023
Priority date	Mar 28, 2023
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

Disclosed are a display panel and a display device. The pixel circuit in the display panel includes a control circuit, a drive circuit, and a regulating circuit. The control circuit controls the potential of the coupled control node based on the gate drive signal provided by the gate line and the data signal provided by the data line. The drive circuit drives the light-emitting element to emit light based on the potential of the control node and the drive power signal provided by the drive power line. The regulating circuit adjusts the potential of the control node through the coupling effect based on the drive power signal and the initial power signal provided by the initial power line.

First claim

What is claimed is:

1. A display panel, comprising: a substrate and a plurality of pixels disposed on the substrate, wherein each pixel comprises a pixel circuit and a light-emitting element, wherein the pixel circuit is coupled to the light-emitting element and configured to drive the light-emitting element to emit light, and the pixel circuit comprises: a control circuit coupled respectively to a gate line, a data line, and a control node and configured to control a potential of the control node based on a gate drive signal provided by the gate line and a data signal provided by the data line; a drive circuit with a control terminal coupled to the control node, an input terminal coupled to a drive power line, and an output terminal coupled to the light-emitting element and configured to transmit a drive signal to the light-emitting element based on the potential of the control node and a drive power signal provided by the drive power line to drive the light-emitting element to emit light; a regulating circuit coupled respectively to the drive power line, the control node, and an initial power line and configured, through a coupling effect, to regulate the potential of the control node based on an initial power signal provided by the initial power line and the drive power signal; and wherein the drive circuit comprises a drive transistor, and the regulating circuit comprises at least one regulation capacitor and a storage capacitor, wherein a gate of the drive transistor is coupled to the control node, a first electrode of the drive transistor is coupled to the drive power line, and a second electrode of the drive transistor is coupled to the light-emitting element; the at least one regulation capacitor is connected in series between the drive power line and the control node, and the at least one regulation capacitor is also coupled to the initial power line; and the storage capacitor is connected in series between the drive power line and the control node.

2. The display panel according to claim 1 , further comprising: a semiconductor layer, a first metal layer, and a second metal layer sequentially laminated on a side, distal to the substrate, of the substrate, wherein the semiconductor layer is configured to form a first active layer of the at least one regulation capacitor and a second active layer of the drive transistor; the first metal layer and the second metal layer are respectively configured to form a first capacitor plate and a second capacitor plate of the storage capacitor, the first capacitor plate is coupled to the control node, and the second capacitor plate is coupled to the drive power line, wherein both orthographic projections of the first active layer onto the substrate and the second active layer onto the substrate are overlapped with an orthographic projection of the second capacitor plate onto the substrate.

3. The display panel according to claim 2 , wherein the regulating circuit comprises two regulation capacitors, wherein an overlapping portion between the first active layer and the second capacitor plate is configured to form one regulation capacitor connected in series between the drive power line and the initial power line, and an adjacent portion of the first active layer and the first capacitor plate is configured to form another regulation capacitor connected in series between the initial power line and the control node.

4. The display panel according to claim 2 , wherein the first active layer comprises a first active portion and a second active portion connected in a first direction, wherein an orthographic projection of the second active portion onto the substrate is overlapped with the orthographic projection of the second capacitor plate onto the substrate, and an orthographic projection of the first active portion onto the substrate is not overlapped with the orthographic projection of the second capacitor plate onto the substrate;
the display panel further comprises an insulating layer and a third metal layer that are disposed on a side, distal to the substrate, of the second metal layer, wherein the third metal layer is configured to form a metal portion coupled to the initial power line;
and the metal portion is overlapped with the first active portion through a via hole penetrating the insulating layer, allowing the initial power line to be coupled to the at least one regulation capacitor.

5. The display panel according to claim 4 , wherein an area of the orthographic projection of the first active portion onto the substrate is smaller than an area of the orthographic projection of the second active portion onto the substrate.

6. The display panel according to claim 4 , wherein the metal portion comprises a first metal segment extending along the first direction.

7. The display panel according to claim 4 , wherein the metal portion comprises a second metal segment extending along a second direction, wherein the second direction intersects with the first direction.

8. The display panel according to claim 7 ,
wherein in the first direction, the first active layer and the second active layer are arranged in a staggered manner, and in the second direction, the first active layer and the second active layer are arranged at intervals;
the plurality of pixels are arranged in an array, wherein the first direction represents a pixel row direction, the second direction represents a pixel column direction, and the first direction is perpendicular to the second direction.

9. The display panel according to claim 1 , wherein the control circuit comprises:
a data writing module coupled respectively to the gate line, the data line, and the input terminal of the drive circuit and configured to control connection and disconnection between the data line and the input terminal of the drive circuit based on the gate drive signal;
a light-emitting control module coupled respectively to a light-emitting control line, the drive power line, the input terminal of the drive circuit, the output terminal of the drive circuit, and the light-emitting element and configured to control connection and disconnection between the drive power line and the input terminal of the drive circuit and to control connection and disconnection between the output terminal of the drive circuit and the light-emitting element based on a light-emitting control signal provided by the light-emitting control line;
a compensation module coupled respectively to a compensation control line, the output terminal of the drive circuit, and the control node and configured to control connection and disconnection between the output terminal of the drive circuit and the control node based on a compensation control signal provided by the compensation control line; and
a first reset module coupled respectively to a first reset control line, a first reset power line, and the control node and configured to control connection and disconnection between the first reset power line and the control node based on a first reset control signal provided by the first reset control line.

10. The display panel according to claim 9 , wherein the compensation control line and the gate line are independent of each other; within a refresh cycle, a period for the compensation control line providing a compensation control signal of an active potential is overlapped with a period for the first reset control line providing a first reset control signal of an active potential, and a number of times that the compensation control line provides the compensation control signal of the active potential and a number of times that the first reset control line provides the first reset control signal of the active potential are both greater than or equal to 3,
wherein the compensation c

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Wang Miao
• Guo Yonglin
• Cao Dan
• Liu Cong
• Wang Binyan
• Gao Wenhui
• Yu Ziyang
• Jiang Zhiliang

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3225

  using an active matrix · CPC title