Pixel circuit

Patent metadata

Field	Value
Publication number	US-12347367-B1
Application number	US-202418884121-A
Country	US
Kind code	B1
Filing date	Sep 13, 2024
Priority date	Mar 4, 2024
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A pixel circuit is provided. The pixel circuit includes: a light-emitting element, a driving circuit, a capacitor, a first compensation circuit, a second compensation circuit, a reset read circuit, a data writing circuit, and a light-emitting control circuit. The light-emitting element has a cathode that receives a system low voltage. The driving circuit provides a driving current based on a gate voltage. The capacitor is coupled between a gate control node and a control node. The first compensation circuit provides a system high voltage to the control node and the driving circuit. The second compensation circuit provides a reference voltage to the driving circuit. The reset read circuit provides an initial voltage to the control node and the gate control node. The data writing circuit provides a data signal to the gate control node. The light-emitting control circuit provides the driving current to the light-emitting element.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a light-emitting element, having an anode and a cathode that receives a system low voltage;
a driving circuit, configured to receive a gate voltage of a gate control node to provide a driving current based on the gate voltage;
a capacitor, coupled between the gate control node and a control node;
a first compensation circuit, configured to receive a system high voltage and a light-emitting signal, and coupled to the control node and the driving circuit to provide the system high voltage to the control node and the driving circuit based on the light-emitting signal;
a second compensation circuit, configured to receive a reference voltage and a compensation signal, and coupled to the driving circuit to provide the reference voltage to the driving circuit based on the compensation signal;
a reset read circuit, configured to receive an initial voltage, and coupled to the control node and the gate control node to receive a reset signal, and provide the initial voltage to the control node and the gate control node based on the reset signal;
a data writing circuit, configured to receive a data signal and a writing signal, and coupled to the gate control node to provide the data signal to the gate control node based on the writing signal; and
a light-emitting control circuit, coupled between the driving circuit and the anode of the light-emitting element, and configured to receive the light-emitting signal to transmit the driving current to the anode of the light-emitting element based on the light-emitting signal.

2. The pixel circuit according to claim 1 , wherein the first compensation circuit comprises:
a first transistor, having a first terminal that receives the system high voltage, a control terminal that receives the light-emitting signal, and a second terminal coupled to the driving circuit to provide the system high voltage; and
a second transistor, having a first terminal coupled to the control node, a control terminal that receives the light-emitting signal, and a second terminal coupled to the second terminal of the first transistor.

3. The pixel circuit according to claim 2 , wherein the driving circuit comprises:
a third transistor, having a first terminal coupled to the second terminal of the first transistor, a control terminal coupled to the gate control node, and a second terminal that provides the driving current.

4. The pixel circuit according to claim 3 , wherein the second compensation circuit comprises:
a fourth transistor, having a first terminal coupled to the first terminal of the third transistor, a control terminal that receives the compensation signal, and a second terminal that receives the reference voltage; and
a fifth transistor, having a first terminal coupled to the gate control node, a control terminal that receives the compensation signal, and a second terminal coupled to the second terminal of the third transistor.

5. The pixel circuit according to claim 4 , wherein the light-emitting control circuit comprises:
a sixth transistor, having a first terminal coupled to the second terminal of the third transistor, a control terminal that receives the light-emitting signal, and a second terminal coupled to the anode of the light-emitting element.

6. The pixel circuit according to claim 5 , wherein the data writing circuit comprises:
a seventh transistor, having a first terminal that receives the data signal, a control terminal that receives the writing signal, and a second terminal coupled to the gate control node.

7. The pixel circuit according to claim 6 , wherein the reset read circuit comprises:
an eighth transistor, having a first terminal coupled to the gate control node, a control terminal that receives the reset signal, and a second terminal that receives the initial voltage; and
a ninth transistor, having a first terminal coupled to the control node, a control terminal that receives a control signal or the compensation signal, and a second terminal that receives the initial voltage.

8. The pixel circuit according to claim 7 , wherein the reset read circuit further comprises:
a tenth transistor, having a first terminal coupled to the control node, a control terminal that receives the reset signal, and a second terminal that receives the initial voltage,
wherein the control terminal of the ninth transistor receives the compensation signal.

9. The pixel circuit according to claim 8 , wherein the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the tenth transistor are P-type transistors.

10. The pixel circuit according to claim 7 , wherein an enabling period of the control signal overlaps a sum of enabling periods of the reset signal and the compensation signal.

11. The pixel circuit according to claim 1 , wherein the reset signal, the compensation signal, and the writing signal are sequentially enabled in different periods.

12. The pixel circuit according to claim 1 , wherein the light-emitting element comprises a micro light-emitting diode.

Assignees

• Auo Corp

Inventors

• Lin Wei-Li

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title