Shift register units, gate driver circuits, and display devices

Patent metadata

Field	Value
Publication number	US-12347361-B2
Application number	US-202118290792-A
Country	US
Kind code	B2
Filing date	Nov 22, 2021
Priority date	Nov 22, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

The present disclosure provides a shift register unit, a gate driver circuit, and a display device, belonging to the field of display technology, which can solve the problem of unstable threshold voltage and current leakage of thin film transistors in existing shift register units. The shift register unit in the present disclosure includes: an input subcircuit, an output subcircuit, a pull-down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit, a first auxiliary control subcircuit, and a second auxiliary control subcircuit. The first auxiliary control subcircuit is configured to write the third reference level signal to the pull-down control node when the pull-down node is the first reference level signal, and control the pull-down subcircuit to be closed to control the first noise reduction subcircuit to be open.

First claim

The invention claimed is:

1. A shift register unit, comprising an input subcircuit, an output subcircuit, a pull -down control subcircuit, a pull-down subcircuit, a first noise reduction subcircuit, a first auxiliary control subcircuit, and a second auxiliary control subcircuit; wherein
the input subcircuit is configured to, in response to an input signal from a signal input terminal, raise a potential of a pull-up node through the input signal, wherein the pull-up node is simultaneously connected to at least the input subcircuit, the output subcircuit, and the first noise reduction subcircuit;
the output subcircuit is configured to, in response to a pulled-up potential of the pull-up node, output a signal through a signal output terminal;
the pull-down control subcircuit is configured to, in response to a first power supply voltage signal, control a potential of a pull-down node through the first power supply voltage signal, wherein the pull-down node is simultaneously connected to at least the pull-down control subcircuit, the pull-down subcircuit, and the first noise reduction subcircuit;
the pull-down subcircuit is configured to, in response to a potential of a pull-down control node, pull down the potential of the pull-down node through a first reference level signal, wherein the pull-down control node is simultaneously connected to at least the pull-down subcircuit, the first auxiliary control subcircuit, and the second auxiliary control subcircuit;
the first noise reduction subcircuit is configured to, in response to the potential of the pull -down node, denoise a potential of the pull-up node through a second reference level signal;
the first auxiliary control subcircuit is configured to, when the pull-down node is the first reference level signal, write a third reference level signal to the pull-down control node, and control the pull-down subcircuit to be closed to control the first noise reduction subcircuit to be open; and
the second auxiliary control subcircuit is configured to, when the pull-down node is the first power voltage signal, write the first reference level signal to the pull-down control node, and control the pull-down subcircuit to be open to control the first noise reduction subcircuit to denoise the pull-up node through the second reference level signal.

2. The shift register unit according to claim 1 , wherein
the first auxiliary control subcircuit comprises a first storage capacitor, wherein one end of the first storage capacitor is connected to the pull-down control node, and the other end of the first storage capacitor is connected to a first power supply voltage terminal, wherein the pull -down control node is connected to the input subcircuit; and
the second auxiliary control subcircuit comprises a ninth transistor and a tenth transistor, wherein a control electrode of the ninth transistor is connected to an auxiliary control terminal, a first electrode of the ninth transistor is connected to a first reference level terminal, and a second electrode of the ninth transistor is connected to the pull-down control node, and a control electrode of the tenth transistor is connected to the pull-down node, a first electrode of the tenth transistor is connected to the first reference level terminal, and a second electrode of the tenth transistor is connected to the pull-down control node.

3. The shift register unit according to claim 1 , wherein
the first auxiliary control subcircuit comprises an eleventh transistor, wherein a control electrode and a first electrode of the eleventh transistor are connected to the signal input terminal, and a second electrode of the eleventh transistor is connected to the pull-down control node; and
the second auxiliary control subcircuit comprises a twelfth transistor and a thirteenth transistor, wherein a control electrode of the twelfth transistor is connected to an auxiliary control terminal, a first electrode of the twelfth transistor is connected to a first reference level terminal, and the second electrode of the twelfth transistor is connected to the pull-down control node, and a control electrode of the thirteenth transistor is connected to the pull-down node, a first electrode of the thirteenth transistor is connected to the first reference level terminal, and a second electrode of the thirteenth transistor is connected to the pull-down control node.

4. The shift register unit according to claim 1 , wherein
the first auxiliary control subcircuit comprises a fourteenth transistor, wherein a control electrode and a first electrode of the fourteenth transistor are connected to a first power supply voltage terminal, and a second electrode of the fourteenth transistor is connected to the pull-down control node; and
the second auxiliary control subcircuit comprises a fifteenth transistor and a sixteenth transistor, wherein a control electrode of the fifteenth transistor is connected to the pull-down node, a first electrode of the fifteenth transistor is connected to a first reference level terminal, and a second electrode of the fifteenth transistor is connected to the pull-down control node, and a control electrode of the sixteenth transistor is connected to an auxiliary control terminal, a first electrode of the sixteenth transistor is connected to the first reference level terminal, and a second electrode of the sixteenth transistor is connected to the pull-down control node.

5. The shift register unit according to claim 1 , wherein the shift register unit further comprises a second noise reduction subcircuit, wherein the second noise reduction subcircuit is configured to, in response to the potential of the pull-down node, denoise a potential of the signal output terminal through the second reference level signal.

6. The shift register unit according to claim 5 , wherein the second noise reduction subcircuit comprises a fourth transistor, wherein a control electrode of the fourth transistor is connected to the pull-down node, a first electrode of the fourth transistor is connected to a second reference level terminal, and a second electrode of the fourth transistor is connected to the signal output terminal.

7. The shift register unit according to claim 1 , wherein the shift register unit further comprises a reset subcircuit, wherein the reset subcircuit is configured to, in response to a reset signal, reset a potential of the pull-up node through the second reference level signal.

8. The shift register unit according to claim 7 , wherein the reset subcircuit comprises a second transistor, wherein a control electrode of the second transistor is connected to a reset signal terminal, a first electrode of the second transistor is connected to a second reference level terminal, and a second electrode of the second transistor is connected to the pull-up node.

9. The shift register unit according to claim 1 , wherein the input subcircuit comprises a first transistor, wherein a control electrode and a first electrode of the first transistor are connected to the signal input terminal, and the second electrode of the first transistor is connected to the pull-up node.

10. The shift register unit according to claim 1 , wherein the output subcircuit comprises a third transistor and a second storage capacitor, wherein
a control electrode of the third transistor is connected to the pull-up node, a first electrode of the third transistor is connected to a clock signal terminal, and a second electrode of the third transistor is connected to the signal output terminal; and
one end of the second storage capacitor is connected to the pull-up node, and the other end of the second storage capacitor is connected to the signal output terminal.

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Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd

Inventors

• Ren Jinyu
• Liu Haisheng
• Peng Kuanjun
• Zhang Fangzhen
• Wang Jinqian
• Ma Guojing
• Wang Dan
• Wang Wei
• Feng Sha

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title