Systems and methods for managing interrupt priority levels

Patent metadata

Field	Value
Publication number	US-12346722-B2
Application number	US-202218073075-A
Country	US
Kind code	B2
Filing date	Dec 1, 2022
Priority date	Dec 7, 2021
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A system includes non-transitory computer readable memory and a processor. The non-transitory computer readable memory stores a current processor interrupt priority level and a current disable interrupt control (DISICTL) interrupt priority level. The processor to update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions, and update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level. The processor determines a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level, and apply the highest interrupt priority level during execution of respective code.

First claim

The invention claimed is:

1. A system, comprising:
non-transitory computer readable memory storing:
a current processor interrupt priority level;
a current disable interrupt control (DISICTL) interrupt priority level; and

a processor to:
update the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions;
update the current DISICTL interrupt priority level based on a respective DISICTL instruction, wherein the respective DISICTL instruction specifies a respective user-definable DISICTL interrupt priority level; and
disable exceptions having a respective associated interrupt priority level equal to or lower than a highest interrupt priority level between the current processor interrupt priority level and the current DISICTL interrupt priority level during execution of respective code.

2. The system of claim 1 , wherein the processor includes a processor stack storing at least one prior processor interrupt priority level.

3. The system of claim 1 , wherein the non-transitory computer readable memory comprises:
at least one first register in the processor storing the current processor interrupt priority level; and
at least one second register in the processor storing the current DISICTL interrupt priority level.

4. The system of claim 1 , wherein the respective DISICTL instruction specifying the respective user-definable DISICTL interrupt priority level comprises the respective DISICTL instruction specifying a value of the user-definable DISICTL interrupt priority level.

5. The system of claim 1 , wherein the respective DISICTL instruction specifying the respective user-definable DISICTL interrupt priority level comprises the respective DISICTL instruction specifying a memory location of a prior DISICTL interrupt priority level.

6. The system of claim 1 , wherein:
the respective DISICTL instruction specifies (a) a respective user-definable DISICTL interrupt priority level and (b) a storage destination; and
the processor to execute the respective DISICTL instruction, including to:
update the current DISICTL interrupt priority level from a prior DISICTL interrupt priority level to the respective user-definable DISICTL interrupt priority level specified in the respective DISICTL instruction; and
store the prior DISICTL interrupt priority level in the storage destination specified in the respective DISICTL instruction.

7. The system of claim 1 , wherein the processor to:
execute the respective DISICTL instruction specifying the respective user-definable DISICTL interrupt priority level, wherein execution of the respective DISICTL instruction includes to update the current DISICTL interrupt priority level from a prior DISICTL interrupt priority level to the respective user-definable DISICTL interrupt priority level specified in the respective DISICTL instruction.

8. The system of claim 7 , wherein:
execution of the respective DISICTL instruction includes to store the prior DISICTL interrupt priority level; and
the processor to, after the execution of a first piece of the respective code associated with the respective DISICTL instruction, to restore the stored prior DISICTL interrupt priority level as the current DISICTL interrupt priority level.

9. The system of claim 8 , wherein the non-transitory computer readable memory comprises:
a first memory location storing the current processor interrupt priority level;
a second memory location storing the current DISICTL interrupt priority level; and
a third memory location storing the prior DISICTL interrupt priority level.

10. The system of claim 7 , wherein the processor to:
after executing a portion of a first piece of the respective code, execute a second DISICTL instruction specifying a second user-definable DISICTL interrupt priority level to update the current DISICTL interrupt priority level to the second user-definable DISICTL interrupt priority higher than the respective user-definable DISICTL interrupt priority level;
disable exceptions having a respective associated interrupt priority level equal to or lower than the second user-definable DISICTL interrupt priority level during execution of a second piece of the respective code;
after the execution of the second piece of the respective code, restore the current DISICTL interrupt priority level to the respective user-definable DISICTL interrupt priority level; and
continue execution of the first piece of the respective code.

11. A system, comprising:
non-transitory computer readable memory including:
a first memory location for storing a current disable interrupt control (DISICTL) interrupt priority level; and
a second memory location for storing a prior DISICTL interrupt priority level, and

a processor to:
store a first DISICTL interrupt priority level associated with a first DISICTL instruction as the current DISICTL interrupt priority level in the first memory location;
disable exceptions having a respective associated interrupt priority level equal to or lower than the first DISICTL interrupt priority level during execution of a first piece of code; and
execute a second DISICTL instruction specifying a second DISICTL interrupt priority level, wherein execution of the second DISICTL instruction includes:
store the second DISICTL interrupt priority level specified by the second DISICTL instruction as the current DISICTL interrupt priority level in the first memory location;
store the first DISICTL interrupt priority level as the prior DISICTL interrupt priority level in the second memory location; and
disable exceptions having a respective associated interrupt priority level equal to or lower than the second DISICTL interrupt priority level during execution of a second piece of code.

12. The system of claim 11 , wherein:
the second DISICTL instruction specifying the second DISICTL interrupt priority level comprises the second DISICTL instruction specifying the second memory location; and
the processor to store the second DISICTL interrupt priority level specified by the second DISICTL instruction as the current DISICTL interrupt priority level in the first memory location comprises the processor to (a) access the prior DISICTL interrupt priority level stored in the second memory location and (b) store the accessed prior DISICTL interrupt priority level as the current DISICTL interrupt priority level in the first memory location.

13. The system of claim 11 , the processor to:
execute a third DISICTL instruction specifying a third DISICTL interrupt priority level, wherein execution of the third DISICTL instruction includes:
store the third DISICTL interrupt priority level specified by the third DISICTL instruction as the current DISICTL interrupt priority level in the first memory location; and
store the second DISICTL interrupt priority level as the prior DISICTL interrupt priority level in the second memory location; and
disable exceptions having a respective associated interrupt priority level equal to or lower than the third DISICTL interrupt priority level during execution of a third piece of code.

14. A method, comprising:
storing in non-transitory computer readable memory a current processor interrupt priority level;
storing in the non-transitory computer readable memory a current disable interrupt control (DISICTL) interrupt priority level;
updating, by a processor, the current processor interrupt priority level based on respective interrupt priority levels associated with respective exceptions;
updating, by the processor, the current DISICTL interrupt priority level based on a respective DISICT

Assignees

• Microchip Tech Inc

Inventors

• Catherwood Michael
• Schlunder Howard
• Mickey David

Classifications

• G06F8/71

  Version control (security arrangements therefor G06F21/57); Configuration management · CPC title

• G06F9/4831 Primary

  with variable priority · CPC title

• G06F9/4818

  Priority circuits therefor · CPC title

• G06F9/4812

  by interrupt, e.g. masked · CPC title

• G06F13/26 Primary

  with priority control · CPC title