Enabling secure state-clean during configuration of partial reconfiguration bitstreams on FPGA

Patent metadata

Field	Value
Publication number	US-12346489-B2
Application number	US-202318300622-A
Country	US
Kind code	B2
Filing date	Apr 14, 2023
Priority date	Sep 25, 2020
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

An apparatus to facilitate enabling secure state-clean during configuration of partial reconfiguration bitstreams on accelerator devices is disclosed. The apparatus includes a security engine to perform, as part of a PR configuration sequence for a new partial reconfiguration (PR) persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in the region; perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation.

First claim

What is claimed is:

1. An apparatus comprising:
a programmable integrated circuit (IC) to:
perform, as part of a partial reconfiguration (PR) configuration sequence for a new PR persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in a region, wherein the first clear operation is publicly authenticable;
perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and
perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation,
wherein the first clear operation is persona independent while the set operation and the second clear operation are persona dependent.

2. The apparatus of claim 1 , wherein ownership for the region is defined via one or more masks created for the region.

3. The apparatus of claim 1 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated, and wherein the second clear operation performed using a persona-dependent mask corresponding to the new PR persona.

4. The apparatus of claim 3 , wherein the persona-independent mask is not under control of a tenant of the apparatus.

5. The apparatus of claim 1 , wherein the second clear operation is performed by loading the memory blocks with zeros.

6. The apparatus of claim 1 , wherein the new PR persona comprises a PR bitstream used to configure the region.

7. The apparatus of claim 1 , wherein the apparatus comprises a memory coupled to the programmable IC.

8. The apparatus of claim 1 , wherein the programmable IC comprises at least one of a field programmable gate array (FPGA), a programmable array logic (PAL), a programmable logic array (PLA), a field programmable logic array (FPLA), an electrically programmable logic device (EPLD), an electrically erasable programmable logic device (EEPLD), a logic cell array (LCA), or a complex programmable logic devices (CPLD).

9. A method comprising:
performing, as part of a partial reconfiguration (PR) configuration sequence for a new PR persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in a region;
performing, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and
performing, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation,
wherein the first clear operation is persona independent while the set operation and the second clear operation are persona dependent.

10. The method of claim 9 , wherein ownership of the region is defined by a corresponding region-ownership mask.

11. The method of claim 9 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated, and wherein the persona-independent mask is not under control of a tenant.

12. The method of claim 9 , wherein the second clear operation performed using a persona-dependent mask corresponding to the new PR persona, and wherein the second clear operation is performed by loading the memory blocks with zeros.

13. The method of claim 9 , wherein the new PR persona comprises a PR bitstream used to configure the region.

14. The method of claim 9 , wherein the region is included in a PR region allowlist and provides an environment for a tenant to prevent interference from other tenants.

15. A non-transitory machine-readable storage medium comprising instructions that, when executed, cause at least one processor to at least:
perform, as part of a partial reconfiguration (PR) configuration sequence for a new PR persona corresponding to a PR bitstream, a first clear operation to clear previously-set persona configuration bits in a region;
perform, as part of the PR configuration sequence subsequent to the first clear operation, a set operation to set new persona configuration bits in the region; and
perform, as part of the PR configuration sequence, a second clear operation to clear memory blocks of the region that became unfrozen subsequent to the set operation,
wherein the first clear operation is persona independent while the set operation and the second clear operation are persona dependent.

16. The non-transitory machine-readable storage medium of claim 15 , wherein ownership of the region is defined by a corresponding region-ownership mask.

17. The non-transitory machine-readable storage medium of claim 15 , wherein the first clear operation is performed using a persona-independent mask that is publicly authenticated, and wherein the persona-independent mask is not under control of a tenant.

18. The non-transitory machine-readable storage medium of claim 15 , wherein the second clear operation is performed using a persona-dependent mask corresponding to the new PR persona, and wherein the second clear operation is performed by loading the memory blocks with zeros.

19. The non-transitory machine-readable storage medium of claim 15 , wherein the new PR persona comprises a PR bitstream used to configure the region.

20. The non-transitory machine-readable storage medium of claim 15 , wherein the region is included in a PR region allowlist and provides an environment for a tenant to prevent interference from other tenants.

Assignees

• Intel Corp

Inventors

• Trivedi Alpa
• Weber Scott
• Schulz Steffen
• Koeberl Patrick

Classifications

• G06F11/3051

  Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247) · CPC title

• G06F11/3058

  Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206) · CPC title

• G06F11/0754

  by exceeding limits · CPC title

• G06F15/7867

  with reconfigurable architecture · CPC title

• G06F21/575

  Secure boot · CPC title