Reduced common mode voltage pulse width modulation switching scheme with capacitor voltage balancing for a multilevel power converter

Patent metadata

Field	Value
Publication number	US-12346184-B2
Application number	US-202318307375-A
Country	US
Kind code	B2
Filing date	Apr 26, 2023
Priority date	Jan 19, 2023
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

A multilevel power converter includes a plurality of switches, a first DC link capacitor, a second DC link capacitor, and one or more processors configured to: generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme; modify the pulse width modulated pulse pattern to render a modified pulse pattern; and cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance voltages at the first DC link capacitor and the second DC link capacitor.

First claim

What is claimed is:

1. A multilevel power converter for an aircraft, comprising:
a plurality of switches;
a first direct current (DC) link capacitor;
a second DC link capacitor; and
one or more processors configured to:
generate, for a duty cycle of the multilevel power converter, a pulse width modulated pulse pattern in accordance with a reduced common mode voltage scheme;
modify the pulse width modulated pulse pattern to render a modified pulse pattern by delaying in time or advancing in time at least one of a falling edge or a rising edge of a pulse of a pulse width modulated signal of the pulse width modulated pulse pattern; and
cause the plurality of switches to implement the duty cycle based at least in part on the modified pulse pattern to render a common mode voltage pulse to balance a first voltage at the first DC link capacitor with a second voltage at the second DC link capacitor.

2. The multilevel power converter of claim 1 , wherein the one or more processors configured to:
receive the first voltage associated with the first DC link capacitor;
receive the second voltage associated with the second DC link capacitor; and
determine a voltage error based at least in part on the first voltage and the second voltage, and
wherein in modifying the pulse width modulated pulse pattern, the one or more processors are configured to adjust the pulse of the pulse width modulated signal of the pulse width modulated pulse pattern based at least in part on one or more characteristics of the voltage error.

3. The multilevel power converter of claim 2 , wherein the one or more characteristics of the voltage error include a magnitude and a polarity of the voltage error.

4. The multilevel power converter of claim 3 , wherein the common mode voltage pulse rendered has a polarity that is based at least in part on the polarity of the voltage error.

5. The multilevel power converter of claim 3 , wherein the common mode voltage pulse rendered has a width that is based at least in part on the magnitude of the voltage error.

6. The multilevel power converter of claim 3 , wherein the common mode voltage pulse is one of a number of common mode voltage pulses rendered, and wherein the number of common mode voltage pulses rendered is either one or a plurality depending on the polarity and/or the magnitude of the voltage error.

7. The multilevel power converter of claim 2 , wherein in adjusting the pulse of the pulse width modulated signal of the pulse width modulated pulse pattern, the one or more processors are configured to delay in time at least one of the rising edge or the falling edge of the pulse.

8. The multilevel power converter of claim 2 , wherein in adjusting the pulse of the pulse width modulated signal of the pulse width modulated pulse pattern, the one or more processors are configured to advance in time at least one of the rising edge or the falling edge of the pulse.

9. The multilevel power converter of claim 2 , wherein the pulse width modulated signal is one of a plurality of pulse width modulated signals of the pulse width modulated pulse pattern, and wherein in modifying the pulse width modulated pulse pattern, the one or more processors are configured to adjust a pulse of each one of the plurality of pulse width modulated signals,
wherein the common mode voltage pulse rendered is one of a plurality of common mode voltage pulses rendered, and
wherein a number of common mode voltage pulses of the plurality of common mode voltage pulses rendered is equal to a number of pulse width modulated signals of the plurality of pulse width modulated signals.

10. The multilevel power converter of claim 2 , wherein the pulse width modulated signal is one of a plurality of pulse width modulated signals of the pulse width modulated pulse pattern, and wherein in modifying the pulse width modulated pulse pattern, the one or more processors are configured to adjust a pulse of each one of the plurality of pulse width modulated signals, and
wherein the common mode voltage pulse rendered is one of at least two common mode voltage pulses rendered.

11. The multilevel power converter of claim 2 , wherein the common mode voltage pulse rendered is one of a number of common mode voltage pulses rendered, and wherein the pulse width modulated signal is one of a number of pulse width modulated signals of the pulse width modulated pulse pattern, and
wherein in modifying the pulse width modulated pulse pattern, the one or more processors are configured to adjust a pulse of each pulse width modulated signal of the pulse width modulated pulse pattern so that the number of common mode voltage pulses rendered is at least one less than the number of pulse width modulated signals in the pulse width modulated pulse pattern.

12. The multilevel power converter of claim 2 , wherein in modifying the pulse width modulated pulse pattern, the one or more processors are configured to adjust both the falling edge and the rising edge of the pulse of the pulse width modulated signal.

13. The multilevel power converter of claim 2 , wherein the one or more processors are further configured to:
determine whether a magnitude of the voltage error is within a predetermined range, and
wherein when the magnitude of the voltage error is not within the predetermined range, the pulse width modulated pulse pattern is modified to render the modified pulse pattern so that the pulse of the pulse width modulated signal is adjusted, and
wherein when the magnitude of the voltage error is within the predetermined range, the pulse width modulated pulse pattern is not modified and the plurality of switches are caused to implement the duty cycle based at least in part on the pulse width modulated pulse pattern.

14. The multilevel power converter of claim 2 , wherein the one or more processors are further configured to:
determine whether a magnitude of the voltage error is within a first predetermined range or within a second predetermined range, and
wherein when the magnitude of the voltage error is within the first predetermined range or the second predetermined range, the pulse width modulated pulse pattern is modified to render the modified pulse pattern so that the pulse of the pulse width modulated signal is adjusted, wherein the pulse of the pulse width modulated signal is adjusted so that more common mode voltage is injected when the magnitude of the voltage error is within the first predetermined range than when the magnitude of the voltage error is within the second predetermined range.

15. The multilevel power converter of claim 2 , wherein in adjusting the pulse of the pulse width modulated signal of the pulse width modulated pulse pattern, the one or more processors are configured to delay and/or advance in time the rising edge and/or the falling edge of the pulse by correlating a magnitude of the voltage error to a predefined time for the delay and/or advance that is pre-programmed in control logic or looked up in a look up table.

16. The multilevel power converter of claim 1 , further comprising:
a first rail;
a second rail;
a mid rail; and
a DC link electrically coupling the first rail and the second rail, the first DC link capacitor and the second DC link capacitor being positioned along the DC link, the mid rail being electrically coupled with the DC link between the first DC link capacitor and the second DC link capacitor.

17. The multilevel power converter of claim 1 , wherein the voltages at the first DC link capacitor and at the second DC link capacitor are balanced so that the voltages are equal o

Assignees

• Gen Electric

Inventors

• Huh Kum Kang
• Ittamveettil Hridya
• Garces Luis J
• Datta Rajib
• Pan Di
• Wang Yukai

Classifications

• G06F1/3203

  Power management, i.e. event-based initiation of a power-saving mode · CPC title

• H02M7/797

  using semiconductor devices only · CPC title

• H02M1/0043

  Converters switched with a phase shift, i.e. interleaved (non-isolated DC/DC converters H02M3/1586) · CPC title

• B64D41/00 Primary

  Power installations for auxiliary purposes · CPC title

• H02M7/217

  using semiconductor devices only · CPC title