Driver circuit

Patent metadata

Field	Value
Publication number	US-12345965-B2
Application number	US-202018006124-A
Country	US
Kind code	B2
Filing date	Jul 21, 2020
Priority date	Jul 21, 2020
Publication date	Jul 1, 2025
Grant date	Jul 1, 2025

Abstract

An embodiment includes an output circuit with transistors and a withstand voltage protection circuit. The withstand voltage protection circuit includes resistors connected between an output signal terminal on the positive phase side and an output signal terminal on the negative phase side. A switch includes an NMOS transistor having a gate terminal connected to the connection point of the resistors, a drain terminal connected to the bias voltage, and a source terminal connected to the base terminal of the transistor.

First claim

The invention claimed is:

1. A driver circuit comprising:
an open collector type output circuit configured to drive an optical modulator connected to a first output signal terminal on a positive phase side and a second output signal terminal on a negative phase side of the driver circuit, wherein the open collector type output circuit includes:
a first transistor and a second transistor having a base terminal to which a differential signal configured to drive the optical modulator is input;
a third transistor having a base terminal connected to a first bias voltage, a collector terminal connected to the first output signal terminal, and an emitter terminal connected to a collector terminal of the first transistor;
a fourth transistor having a base terminal connected to the first bias voltage, a collector terminal connected to the second output signal terminal, and an emitter terminal connected to the collector terminal of the second transistor;
a fifth transistor having a collector terminal connected to emitter terminals of the first and second transistors, an emitter terminal connected to ground, the first transistor being configured to flow currents through the first, second, third, and fourth transistors in accordance with a second bias voltage applied to the base terminal; and
a withstand voltage protection circuit configured to control currents flowing through the first, second, third and fourth transistors in accordance with a common voltage between the first output signal terminal and the second output signal terminal, wherein the withstand voltage protection circuit includes:

first and second resistors connected in series between the first output signal terminal and the second output signal terminal, and
a switch connected between the second bias voltage and the base terminal of the fifth transistor, and
the switch is turned off when a connection point of the first and second resistors is a floating voltage or a ground voltage, and is turned on when the connection point of the first and second resistors is a voltage higher than the ground voltage.

2. The driver circuit according to claim 1 , wherein the withstand voltage protection circuit further includes:
a third resistor having one end connected to the connection point of the first and second resistors, and
a fourth resistor having one end connected to the other end of the third resistor and the other end connected to ground, and
the switch comprises an NMOS transistor having a gate terminal connected to a connection point of the third and fourth resistors, a drain terminal connected to the second bias voltage, and a source terminal connected to the base terminal of the fifth transistor.

3. A driver circuit comprising:
an open collector type output circuit configured to drive an optical modulator connected to a first output signal terminal on a positive phase side and a second output signal terminal on a negative phase side of the driver circuit, wherein the open collector type output circuit includes:
a first transistor and a second transistor having a base terminal to which a differential signal configured to drive the optical modulator is input;
a third transistor having a base terminal connected to a first bias voltage, a collector terminal connected to the first output signal terminal, and an emitter terminal connected to a collector terminal of the first transistor;
a fourth transistor having a base terminal connected to the first bias voltage, a collector terminal connected to the second output signal terminal, and an emitter terminal connected to the collector terminal of the second transistor;
a fifth transistor having a collector terminal connected to emitter terminals of the first and second transistors, an emitter terminal connected to ground, the first transistor being configured to flow currents through the first, second, third, and fourth transistors in accordance with a second bias voltage applied to the base terminal; and
a withstand voltage protection circuit configured to control currents flowing through the first, second, third and fourth transistors in accordance with a common voltage between the first output signal terminal and the second output signal terminal, wherein the withstand voltage protection circuit includes:

first and second resistors connected in series between the first output signal terminal and the second output signal terminal,
a first switch connected between a power supply voltage of the driver circuit and the first output signal terminal, and
a second switch connected between the power supply voltage and the second output signal terminal, and
the first and second switches are turned on when a connection point of the first and second resistors is a floating voltage or a ground voltage, and is turned off when the connection point between the first and second resistors is a voltage higher than the ground voltage.

4. The driver circuit according to claim 3 , wherein:
the withstand voltage protection circuit further includes a third resistor having one end connected to the connection point of the first and second resistors and the other end connected to ground,
the first switch comprises a first PMOS transistor having a gate terminal connected to the connection point of the first and second resistors, a drain terminal connected to the first output signal terminal, and a source terminal connected to the power supply voltage, and
the second switch comprises a second PMOS transistor having a gate terminal connected to the connection point of the first and second resistors, a drain terminal connected to the second output signal terminal, and a source terminal connected to the power supply voltage.

5. The driver circuit according to claim 3 , wherein the withstand voltage protection circuit further includes:
a fourth resistor connected between the first switch and the first output signal terminal, and
a fifth resistor connected between the second switch and the second output signal terminal.

6. An open collector type output circuit comprising:
a first transistor and a second transistor having a base terminal, a differential input signal connected to the base terminal;
a third transistor having a base terminal connected to a first bias voltage, a collector terminal connected to a first output signal terminal, and an emitter terminal connected to a collector terminal of the first transistor;
a fourth transistor having a base terminal connected to the first bias voltage, a collector terminal connected to a second output signal terminal, and an emitter terminal connected to the collector terminal of the second transistor;
a fifth transistor having a collector terminal connected to emitter terminals of the first and second transistors, an emitter terminal connected to ground, the first transistor being configured to flow currents through the first, second, third, and fourth transistors in accordance with a second bias voltage applied to the base terminal; and
a withstand voltage protection circuit configured to control currents flowing through the first, second, third and fourth transistors in accordance with a common voltage between the first output signal terminal and the second output signal terminal, wherein the withstand voltage protection circuit includes:
first and second resistors connected in series between the first output signal terminal and the second output signal terminal, and
a switch connected between the second bias voltage and the base terminal of the fifth transistor, and
the switch is turned off when a connection point of the first and second resistors is a floating voltage or a ground voltage, and is turned on when the connection point of the first and second resistors is a voltage higher than the ground voltage.

7. The open coll

Assignees

• Nippon Telegraph & Telephone

Inventors

• Jo Teruo
• Nagatani Munehiko
• Nosaka Hideyuki

Classifications

• H02H9/04

  responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title

• G02F1/01

  for the control of the intensity, phase, polarisation or colour  (G02F1/29, G02F1/35 take precedence) · CPC title

• H02H9/044

  Physical layout, materials not provided for elsewhere (varistors H01C7/12; spark-gaps H01T; Ovshinsky devices H10N70/00) · CPC title

• H02H9/046

  responsive to excess voltage appearing at terminals of integrated circuits · CPC title

• G02F1/0121 Primary

  Operation of devices; Circuit arrangements, not otherwise provided for in this subclass · CPC title