Semiconductor devices

Patent metadata

Field	Value
Publication number	US-12342576-B2
Application number	US-202217896523-A
Country	US
Kind code	B2
Filing date	Aug 26, 2022
Priority date	Dec 9, 2021
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A semiconductor device is provided. The semiconductor device includes: a substrate with an active region extending in a first direction; an element isolation layer, adjacent to the active region, in the substrate; a gate electrode on the substrate and extending in a second direction which crosses the first direction; a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode; and a source/drain region provided in a recess of the active region adjacent to the gate electrode, and connected to the plurality of channel layers. In the first direction, the gate electrode has a first length on the active region and a second length, greater than the first length, on the element isolation layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
an element isolation layer, adjacent to the active region, in the substrate;
a gate electrode on the substrate and extending in a second direction which crosses the first direction;
a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode; and
a source/drain region provided in a recess of the active region adjacent to the gate electrode, and connected to the plurality of channel layers,
wherein, in the first direction, the gate electrode has a first length on the active region and a second length, greater than the first length, on the element isolation layer.

2. The semiconductor device of claim 1 , wherein in a plan view, the gate electrode has a first side surface extending linearly in the second direction on the active region and a second side surface that convexly protrudes from the first side surface on the element isolation layer.

3. The semiconductor device of claim 2 , wherein a boundary between the first side surface and the second side surface corresponds to a boundary between the active region and the element isolation layer.

4. The semiconductor device of claim 2 , wherein a boundary between the first side surface and the second side surface is on the element isolation layer and spaced apart from a boundary between the active region and the element isolation layer.

5. The semiconductor device of claim 1 , wherein the second length is in a range of about 1.1 times to about 1.3 times the first length.

6. The semiconductor device of claim 1 , further comprising a gate spacer layer on a side of the gate electrode,
wherein the gate spacer layer has a substantially constant length in the first direction on the active region and the element isolation layer.

7. The semiconductor device of claim 1 , further comprising a gate dielectric layer between the active region and the gate electrode, and between the element isolation layer and the gate electrode,
wherein, in the first direction, the gate dielectric layer has a third length on the active region and a fourth length, greater than the third length, on the element isolation layer.

8. The semiconductor device of claim 1 , wherein an upper surface of the active region is farther from the upper surface of the substrate than an upper surface of the element isolation layer.

9. The semiconductor device of claim 1 , wherein the gate electrode has the first length in the first direction in a region in which the gate electrode overlaps the plurality of channel layers in the third direction.

10. The semiconductor device of claim 1 , wherein the plurality of channel layers do not overlap the element isolation layer in the third direction.

11. The semiconductor device of claim 1 , wherein the gate electrode does not overlap the active region in the third direction in a region in which the gate electrode has the second length.

12. The semiconductor device of claim 1 , further comprising a gate separation layer on a side of the gate electrode.

13. The semiconductor device of claim 1 , further comprising a spacer layer between the gate electrode and the source/drain region.

14. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
an element isolation layer, adjacent to the active region, in the substrate;
a gate electrode on the substrate and extending in a second direction which crosses the first direction;
a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by the gate electrode,
wherein in a plan view, the gate electrode has a convex side surface in a region in which the gate electrode overlaps the element isolation layer.

15. The semiconductor device of claim 14 , wherein in the plan view, the gate electrode has a side surface extending linearly in the second direction in a region in which the gate electrode overlaps the active region.

16. The semiconductor device of claim 14 , wherein the gate electrode has a symmetrical shape based on its center in the first direction.

17. The semiconductor device of claim 14 , wherein in the first direction, the gate electrode has a first length in a region in which the gate electrode overlaps the active region in the third direction, and a second length, greater than the first length, in the region in which the gate electrode overlaps the element isolation layer.

18. The semiconductor device of claim 17 , wherein the gate electrode comprises a plurality of regions having variable lengths in the first direction in the region in which the gate electrode overlaps the element isolation layer, and
wherein the second length is less than each of the variable lengths.

19. A semiconductor device comprising:
a substrate comprising an active region extending in a first direction;
a first gate structure on the substrate and extending in a second direction which crosses the first direction;
a second gate structure on the substrate and extending in the second direction;
a plurality of channel layers on the active region, spaced apart from each other along a third direction perpendicular to an upper surface of the substrate, and surrounded by each of the first gate structure and the second gate structure; and
a source/drain region on the active region between the first gate structure and the second gate structure, and connected to the plurality of channel layers,
wherein, in the first direction, the first gate structure has a first length on the plurality of channel layers, and a second length, greater than the first length, on the outside of the plurality of channel layers.

20. The semiconductor device of claim 19 , wherein, in the first direction, the second gate structure has a third length on the plurality of channel layers, and a fourth length, substantially equal to the third length, outside of the plurality of channel layers.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Son Jinkyung
• Kim Seungje
• Park Jiwon
• Lim Jaepo
• Jo Minseok
• Lim Seunghyun
• Choi Jinyoung

Classifications

• H10D64/018

  Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates · CPC title

• H10D64/017

  using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title