Method for manufacturing semiconductor device and semiconductor device manufactured thereby

Patent metadata

Field	Value
Publication number	US-12342570-B2
Application number	US-202217748016-A
Country	US
Kind code	B2
Filing date	May 18, 2022
Priority date	Dec 27, 2021
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A method for manufacturing a semiconductor device includes forming an N-type layer on the first surface of the N+ type substrate, etching the N-type layer to form a trench, forming a sacrificial layer on an inner bottom surface of the trench, forming a first mask on an inner side of the trench, removing the sacrificial layer, and forming a P type shield region by implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer.

First claim

What is claimed is:

1. A method for manufacturing a semiconductor device, comprising:
forming an N-type layer on a first surface of an N+ type substrate,
forming a P type region in the N-type layer,
etching the P type region and the N-type layer to form a trench,
forming a sacrificial layer on an inner bottom surface of the trench,
forming a first mask on an inner side of the trench,
removing the sacrificial layer, and
implanting ions into an inner surface of the trench exposed by the removal of the sacrificial layer to form a P type shield region,
wherein an upper surface of the sacrificial layer is disposed under an interface between the P type region and the N-type layer, and
wherein a height of a channel is adjusted by adjusting a distance between the upper surface of the sacrificial layer and the interface between the P type region and the N-type layer.

2. The method of claim 1 , wherein
the forming of the trench comprises:
forming a second mask having an opening having a first width on the N-type layer, and then etching the N-type layer to a partial depth using the second mask to form the trench.

3. The method of claim 2 , wherein
the method further comprises forming a source electrode on the N-type layer to be insulated from the gate electrode.

4. The method of claim 1 , wherein
the sacrificial layer fills an interior of the trench from the inner bottom surface of the trench to a partial height of the inner side of the trench.

5. The method of claim 4 , wherein
the sacrificial layer has a height of greater than or equal to about 10 nm.

6. The method of claim 1 , wherein
the forming of the first mask comprises
forming the first mask on the inner side of the trench and the upper surface of the sacrificial layer, and
removing the first mask on the upper surface of the sacrificial layer to expose the sacrificial layer.

7. The method of claim 6 , wherein
the removing of the first mask on the upper surface of the sacrificial layer uses a dry etching method.

8. The method of claim 6 , wherein
the removing of the sacrificial layer uses a wet etching method including phosphoric acid (H 3 PO 3 ).

9. The method of claim 8 , wherein
an etch-rate ratio of the first mask and the sacrificial layer is greater than or equal to about 1:1.5.

10. The method of claim 9 , wherein
the sacrificial layer comprises N x Si y (x, y≥2), and
the first mask comprises SiO 2 .

11. The method of claim 1 , wherein
the forming of the P type shield region uses a tilt ion implantation and a vertical ion implantation method.

12. The method of claim 1 , wherein
the method further comprises forming a first insulating layer on the inner bottom surface and side surface of the trench and on the P type region.

13. The method of claim 1 , wherein
the method further comprises forming a second insulating layer on a gate electrode after forming the gate electrode inside the trench.

14. The method of claim 1 , wherein
the method further comprises forming an N+ type region in the P type region and on a side surface of the trench.

15. The method of claim 1 , wherein
the method further comprises forming a drain electrode on a second surface of the substrate.

Assignees

• Hyundai Motor Co Ltd
• Kia Corp

Inventors

• Park Junghee
• Chun Dae Hwan
• Hong Jungyeop
• Jung Youngkyun
• Joo Nackyong

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H10P30/22

  using masks · CPC title

• H10D30/0297 Primary

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D62/105

  by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  (IGFETs having LDD or drain extension regions H10D30/601) · CPC title