Data compression and decompression methods and systems

Patent metadata

Field	Value
Publication number	US-12341539-B2
Application number	US-202318224199-A
Country	US
Kind code	B2
Filing date	Jul 20, 2023
Priority date	Jul 21, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A data compression method includes: storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address of the memory module, and identifying the compressed data by using redundant ECC bits to form first identification information.

First claim

What is claimed is:

1. A data compression method, applied to a memory controller, comprising:
storing data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of a memory module from a host; wherein, the first address and the second address are located in the same memory bank of the memory module;
according to a relationship between the first address and the second address, selecting a compression scheme from pre-configured compression schemes, and attempting to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, storing the compressed data into the first address or the second address, and identifying the compressed data by using redundant ERROR CORRECTION CODE (ECC) bits to form first identification information.

2. The data compression method of claim 1 , wherein the first identification information comprises an identification for indicating that the data is compressed, the relationship between the first address and the second address, and the compression method used.

3. The data compression method of claim 2 , wherein the relationship between the first address and the second address comprises: the first address and the second address being located in adjacent rows of the same memory bank, and the first address and the second address being located in non-adjacent rows of the same memory bank.

4. The data compression method of claim 3 , wherein, if the first address and the second address are located in non-adjacent rows of the same memory bank, the first identification information further comprises row address information of the first address or the second address where the compressed data is not stored into.

5. The data compression method of claim 1 , wherein the pre-configured compression schemes comprise:
a scheme for compressing data of two adjacent addresses in the same memory bank, and a scheme for compressing data of two non-adjacent addresses in the same memory bank.

6. The data compression method of claim 1 , further comprising:
if the attempt to compress fails, storing the data to be written into the first address and the second address into the first address and the second address, respectively, and identifying the data stored into the first address and the data stored into the second address respectively by using respective redundant ECC bits to form second identification information.

7. The data compression method of claim 6 , wherein the second identification information comprises an identification for indicating that data is not compressed.

8. A data decompression method, applied to a memory controller, comprising:
reading data from a first address or a second address of a memory module in response to a read request for data of the first address or the second address from a host;
if first identification information is identified according to redundant ERROR CORRECTION CODE (ECC) bit identification in the first address or the second address, decompressing the data read from the first address or the second address according to the first identification information to obtain decompressed data of the first address and the second address;
storing the decompressed data of the first address and the second address into a data buffer, and returning the data of corresponding address to the host according to the read request from the host.

9. The data decompression method of claim 8 , wherein, after storing the decompressed data into the data buffer, the method further comprises:
in response to the read request for data of the first address or the second address from the host;
retrieving and sending the data of the first address or the second address from the data buffer to the host.

10. The data decompression method of claim 8 , wherein the first identification information comprises an identification for indicating that the data is compressed, a relationship between the first address and the second address, and a compression method used.

11. The data decompression method of claim 10 , wherein the relationship between the first address and the second address comprises: the first address and the second address being located in adjacent rows of the same memory bank, and the first address and the second address being located in non-adjacent rows of the same memory bank.

12. The data decompression method of claim 11 , wherein, if the first address and the second address are located in non-adjacent rows of the same memory bank, the first identification information further comprises row address information of the first address or the second address where the compressed data is not stored into.

13. The data decompression method of claim 8 , wherein, if second identification information is identified according to redundant ECC bit identification in the first address or the second address, returning the data read from the first address or the second address to the host.

14. The data decompression method of claim 13 , wherein the second identification information comprises an identification for indicating that data is not compressed.

15. A data compression system comprising a memory module and a memory controller, wherein the memory controller comprises:
a receiving module, configured to store data to be written into a first address and a second address into a data buffer in response to a data write request to the first address and the second address of the memory module from a host; wherein, the first address and the second address are located in the same memory bank of the memory module;
a compression processing logic module, configured to select a compression scheme from pre-configured compression schemes according to a relationship between the first address and the second address, and attempt to compress the data to be written into the first address and the second address into compressed data that can be stored into either the first address or the second address by using a pre-defined compression method, if the attempt to compress successes, store the compressed data into the first address or the second address, and identify the compressed data stored into the first address or the second address by using redundant ERROR CORRECTION CODE (ECC) bits to form first identification information.

16. The data compression system of claim 15 , wherein the first identification information comprises an identification for indicating that the data is compressed, the relationship between the first address and the second address, and the compression method used.

17. The data compression system of claim 16 , wherein the relationship between the first address and the second address comprises: the first address and the second address being located in adjacent rows of the same memory bank, and the first address and the second address being located in non-adjacent rows of the same memory bank.

18. The data compression system of claim 17 , wherein, if the first address and the second address are located in non-adjacent rows of the same memory bank, the first identification information further comprises row address information of the first address or the second address where the compressed data is not stored into.

19. The data compression system of claim 15 , wherein the pre-configured compression schemes comprise:
a scheme for compressing data of two adjacent addres

Assignees

• Montage Technology Co Ltd

Inventors

• Li Xiaoyan
• Du Zhaohui
• Long Men
• Chao Yang
• Zhong Dajiang

Classifications

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• H03M7/607

  Selection between different types of compressors · CPC title

• H03M7/6047

  Power optimization with respect to the encoder, decoder, storage or transmission · CPC title

• H03M7/30

  Compression (speech analysis-synthesis for redundancy reduction G10L19/00; for image communication H04N); Expansion; Suppression of unnecessary data, e.g. redundancy reduction · CPC title

• G06F21/78

  to assure secure storage of data (address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00) · CPC title