Spin-orbit torque magnetic random access memory circuit and layout thereof

Patent metadata

Field	Value
Publication number	US-12340830-B2
Application number	US-202217707934-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Mar 4, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.

First claim

What is claimed is:

1. A spin-orbit torque magnetic random access memory circuit, comprising:
a read transistor pair with two read transistors in parallel;
a write transistor pair with two write transistors in parallel;
a spin-orbit torque magnetic random access memory unit with a magnetic tunnel junction and a spin-orbit torque layer, wherein one end of said magnetic tunnel junction is connected to a source of said read transistor pair and the other end of said magnetic tunnel junction is connected to said spin-orbit torque layer, and one end of said spin-orbit torque layer is connected to a source line and the other end of said spin-orbit torque layer is connected to a source of said write transistor pair;
a read bit line connected to a drain of said read transistor pair;
a write bit line connected to a drain of said write transistor pair;
a first word line connected to a gate of one of said two read transistors and a gate of one of said two write transistors; and
a second word line connected to a gate of another one of said two read transistors and a gate of another one of said two write transistors.

2. The spin-orbit torque magnetic random access memory circuit of claim 1 , wherein in an operation of writing low state “0” data, an operation voltage is applied from said first word line and said second word line to open said read transistors and said write transistors, and an operation voltage is applied from said write bit line to said source line through said write transistor pair and said spin-orbit torque layer, and said read bit line is in high-resistance state.

3. The spin-orbit torque magnetic random access memory circuit of claim 1 , wherein in an operation of writing high state “1” data, an operation voltage is applied from said first word line and said second word line to open said read transistors and said write transistors, and an operation voltage is applied from said source line to said write bit line through said spin-orbit torque layer and said write transistor pair, and said read bit line is in high-resistance state.

4. The spin-orbit torque magnetic random access memory circuit of claim 1 , wherein in a read operation, an operation voltage is applied from said first word line and said second word line to open said read transistors and said write transistors, and an operation voltage is applied from said read bit line to said source line and said write bit line through said read transistor pair, said magnetic tunnel junction and said spin-orbit torque layer.

5. The spin-orbit torque magnetic random access memory circuit of claim 1 , wherein said magnetic tunnel junction comprises a pinned layer and a free layer, and said free layer is connected with said spin-orbit torque layer.

6. The spin-orbit torque magnetic random access memory circuit of claim 1 , further comprising a sense amplifier connected with said write bit line and said read bit line.

Assignees

• United Microelectronics Corp

Inventors

• Tseng Chun-Yen
• Kuo Yu-Tse
• Wang Shu-Ru
• Wang Jen-Yu
• Huang Li-Ping
• Wu Yi-Ting
• Wu Jia-Rong
• Huang Chun-Hsien

Classifications

• H10N50/80

  Constructional details · CPC title

• H10N50/10

  Magnetoresistive devices · CPC title

• H10B61/22

  of the field-effect transistor [FET] type · CPC title

• G11C11/1655

  Bit-line or column circuits · CPC title

• G11C11/1657

  Word-line or row circuits · CPC title