Electronic device and method controlling signal provided to processor

Patent metadata

Field	Value
Publication number	US-12340726-B2
Application number	US-202318486363-A
Country	US
Kind code	B2
Filing date	Oct 13, 2023
Priority date	Sep 30, 2022
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

An electronic device is provided. The electronic device includes a processor. The electronic device includes a display including a display panel and a display driver circuit that includes memory. The display driver circuit is configured to identify an event for a display on the display panel. The display driver circuit is configured to, in response to the event of a first type that executes the display through the memory, change, at a timing before a reference time from a start timing of a scan for the display, a state of a signal provided from the display driver circuit to the processor from a first state indicating to enable an image transmission to the display driver circuit to a second state indicating to disable the image transmission. The display driver circuit is configured to, in response to the event of a second type that executes the display by bypassing the memory, change, at the start timing, the state of the signal provided from the display driver circuit to the processor from the first state to the second state.

First claim

What is claimed is:

1. An electronic device comprising:
at least one processor comprising processing circuitry; and
a display including a display panel, and display driver circuitry that includes a memory;
wherein the display driver circuitry is configured to:
provide, to the at least one processor, a signal in a first state, the first state of the signal indicating enabling an image transmission from the at least one processor to the display driver circuitry;
identify an event for performing displaying on the display panel;
in case that the displaying according to the event identified while providing the signal in the first state includes scanning performed through the memory, change a state of the signal from the first state to a second state in response to a timing being before a reference time from a start timing of the scanning performed through the memory, the second state of the signal indicating disabling the image transmission; and
in case that the displaying according to the event identified while providing the signal in the first state includes scanning performed by bypassing the memory, change the state of the signal from the first state to the second state in response to a start timing of the scanning performed by bypassing the memory.

2. The electronic device of claim 1 , wherein the display driver circuitry is further configured to change, in response to a completion of the scanning performed through the memory, the state of the signal from the second state to the first state.

3. The electronic device of claim 1 , wherein the display driver circuitry is further configured to change, in response to a completion of the scanning performed by bypassing the memory, the state of the signal from the second state to the first state.

4. The electronic device of claim 1 , wherein the timing, being before the reference time from the start timing of the scanning performed through the memory, is included in a front porch interval of a vertical synchronization signal for the display driver circuitry or an extended front porch interval of the vertical synchronization signal.

5. The electronic device of claim 1 , wherein the scanning performed through the memory is caused based on a refresh rate being provided via the display panel.

6. The electronic device of claim 1 , wherein the scanning performed through the memory is caused based on a previous refresh rate that was provided via the display panel.

7. The electronic device of claim 1 , wherein scanning performed through the memory is caused based on a control command indicating storing an image received from the at least one processor in the memory or indicating enabling the memory.

8. The electronic device of claim 1 , wherein scanning performed by bypassing the memory is caused based on a vertical sync start (VSS) packet received from the at least one processor before an image to be scanned by bypassing the memory is received from the at least one processor.

9. The electronic device of claim 1 , wherein the at least one processor is configured to:
identify the state of the signal provided from the display driver circuitry;
in response to a start timing of a synchronization signal for the image transmission, execute the image transmission, based on the signal in the first state; and
while the signal in the second state is provided, defer the image transmission.

10. The electronic device of claim 9 , wherein the at least one processor is further configured to execute, at the start timing of the synchronization signal, the image transmission deferred while the signal in the second state is provided, based on identifying that the state is changed from the second state to the first state.

11. The electronic device of claim 9 , wherein the synchronization signal is a vertical synchronization signal or an emission synchronization signal.

12. The electronic device of claim 1 , wherein the display driver circuitry is configured to change, while displaying on the display panel is not performed, the state from the second state to the first state, based on a timing of a synchronization signal for the image transmission.

13. The electronic device of claim 12 , wherein the at least one processor is configured to perform the image transmission at the timing of the synchronization signal in response to identifying the state of the signal changed from the second state to the first state.

14. The electronic device of claim 1 , wherein the display driver circuitry is configured to:
provide, to the at least one processor, the signal, based on a refresh rate for the displaying being lower than a reference refresh rate; and
cease to provide, to the at least one processor, the signal, based on the refresh rate being higher than the reference refresh rate.

15. The electronic device of claim 14 , wherein the memory is configured to be disabled while providing the signal to the at least one processor is ceased.

16. An electronic device comprising:
at least one processor comprising processing circuitry; and
a display including a display panel, and a display driver circuitry including a memory,
wherein the display driver circuitry is configured to:
receive, from the at least one processor, an image to be display on the display panel;
display, on the display panel, the image by scanning the image received from the at least one processor;
store, in the memory, the image received from the at least one processor;
while scanning the image received from the at least one processor, provide, to the at least one processor, a signal in a second state, the second state of the signal indicating disabling an image transmission from the at least one processor to the display driver circuitry;
in response to a completion scanning the image for the received from the at least one processor, change a state of the signal from the second state to a first state that indicates enabling the image transmission; and
in response to a timing being before a reference time from a start timing of scanning the image stored in the memory, change the state of the signal from the first state to the second state.

17. The electronic device of claim 16 , wherein the timing, being before the reference time from the start timing of scanning the image stored in the memory, is included in a front porch interval of a vertical synchronization signal for the display driver circuitry or an extended front porch interval of the vertical synchronization signal.

18. The electronic device of claim 16 , wherein the at least one processor is configured to:
identify the state of the signal provided from the display driver circuitry;
execute, in response to a start timing of a synchronization signal for the image transmission, the image transmission, while the signal in the first state is provided; and
defer the image transmission, while the signal in the second state is provided.

19. The electronic device of claim 18 , wherein the at least one processor is further configured to:
while the signal in the second state is provided, obtain another image distinct from the image and defer transmitting, to the display driver circuitry, the other image obtained while the signal in the second state is provided; and
in response to the signal in the first state changed from the second state, transmit, to the display driver circuitry, the other image obtained while the signal in the second state is provided in response to the start timing of the synchronization signal.

20. The electronic device of claim 16 , wherein the disp

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaesung
• Kwon Kyounghwan
• Bae Jongkon
• Kim Donghwy
• Yang Byungduk

Classifications

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G3/20

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title