Device for controlling trapped ions having an electrode circuitry configured for device testing

Patent metadata

Field	Value
Publication number	US-12339329-B2
Application number	US-202217865559-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Jul 15, 2021
Publication date	Jun 24, 2025
Grant date	Jun 24, 2025

Abstract

A device for controlling trapped ions includes a substrate. An electrode structure is disposed on the substrate, the electrode structure including DC electrodes and RF electrodes of an ion trap configured to trap ions in a space above the substrate. A first device terminal is disposed on the substrate, the first device terminal being connected via a first electrode connection line to a specific DC electrode. Further, a second device terminal is disposed on the substrate, the second device terminal being connected via a second electrode connection line to the specific DC electrode.

First claim

What is claimed is:

1. A device for controlling trapped ions, the device comprising:
a substrate;
an electrode structure disposed on the substrate, the electrode structure comprising DC electrodes and RF electrodes of an ion trap configured to trap ions in a space above the substrate;
a first device terminal disposed on the substrate, the first device terminal being connected via a first electrode connection line to a specific DC electrode; and
a second device terminal disposed on the substrate, the second device terminal being connected via a second electrode connection line to the specific DC electrode.

2. The device of claim 1 , wherein the first electrode connection line is connected to a first end of the specific DC electrode and the second electrode connection line is connected to a second end on the opposite side of the specific DC electrode.

3. The device of claim 1 , wherein the first electrode connection line is connected to a first end of the specific DC electrode and the second electrode connection line is connected to the same first end of the specific DC electrode.

4. The device of claim 1 , wherein some or all of the DC electrodes of the ion trap are connected via a respective first electrode connection line to a respective first device terminal and via a respective second electrode connection line to a respective second device terminal.

5. The device of claim 1 , wherein the second device terminal is located on the substrate adjacent to and in an outward direction from the first device terminal.

6. The device of claim 1 , wherein the first device terminal and/or the second device terminal is a wire bond pad or a through-substrate-vias bond pad.

7. The device of claim 1 , wherein a size of at least one of the first device terminal and the second device terminal is equal to or greater than 130 μm×130 μm.

8. The device of claim 1 , further comprising:
a multi-layer metal interconnect formed in the substrate and electrically connected to the electrode structure,
wherein the first electrode connection line forms part of a first layer of the multi-layer metal interconnect and the second electrode connection line forms part of a second layer of the multi-layer metal interconnect.

9. The device of claim 1 , wherein the electrode structure is disposed on a first side of the substrate, and wherein the first device terminal and the second device terminal are disposed on a second side of the substrate opposite the first side.

10. The device of claim 9 , wherein the first device terminal and the second device terminal are implemented by through-substrate-vias.

11. The device of claim 10 , wherein the through-substrate-vias are formed by straight holes running through the substrate.

12. The device of claim 11 , wherein the through-substrate-via that implements the first terminal is aligned with a first end of the specific DC electrode, and wherein the through-substrate-via that implements the second terminal is aligned with a second end of the specific DC electrode.

13. The device of claim 10 , wherein a first one of the through-substrate-vias corresponds to the first electrode connection line and a second one of the through-substrate-vias corresponds to the second electrode connection line.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Roessler Clemens
• Ostermann Thomas
• Rieser Norbert
• Roessler Johanna Elisabeth
• Schmid Siegfried
• Slamnig Walter

Classifications

• H01J3/40

  Arrangements for removing or diverting unwanted particles, e.g. for negative ions or fringing electrons; Arrangements for velocity or mass selection · CPC title

• G01R27/02

  Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant (by measuring phase angle only G01R25/00) · CPC title

• G06N10/70

  Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title

• G06N10/40

  Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control · CPC title

• G01R31/66 Primary

  Testing of connections, e.g. of plugs or non-disconnectable joints (testing for incorrect line connections G01R31/55) · CPC title