Array substrate and display device

Patent metadata

Field	Value
Publication number	US-12336399-B2
Application number	US-202117630211-A
Country	US
Kind code	B2
Filing date	Feb 4, 2021
Priority date	Feb 4, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

The present disclosure provides an array substrate and a display device. The array substrate includes a plurality of initialization signal lines and a plurality of connection lines. The initialization signal lines are arranged in a first conductive layer, extend along a first direction and are arranged at intervals along a second direction; the connection lines are arranged in a second conductive layer, extend along the second direction and are arranged at intervals along the first direction; the first conductive layer and the second conductive layer are an identical layer or different layers; projections of at least one of the initialization signal lines and at least one of the connection lines on the base substrate are intersected and electrically connected, such that the projections of the initialization signal lines and the connection lines on the base substrate form a grid structure.

First claim

What is claimed is:

1. An array substrate, comprising:
a plurality of pixel units arranged in an array, the pixel units comprising a plurality of sub-pixels;
a plurality of initialization signal lines arranged in a first conductive layer on the array substrate, extending along a first direction and arranged at intervals along a second direction, and configured to provide initialization signals to each of the sub-pixels, wherein the first direction and the second direction intersect;
a plurality of connection lines arranged in a second conductive layer on the array substrate, and extending along the second direction and arranged at intervals along the first direction, wherein:
the first conductive layer and the second conductive layer are an identical layer or different layers; and
projections of at least one of the initialization signal lines and at least one of the connection lines on the array substrate intersect and are electrically connected, such that the projections of the initialization signal lines and the connection lines on the array substrate form a grid structure,
wherein the array substrate comprises a base substrate and a first source-drain layer, a second source-drain layer, and an anode layer sequentially stacked on the base substrate.

2. The array substrate according to claim 1 , wherein:
in the first conductive layer and the second conductive layer, at least any one thereof is the first source-drain layer, and the other one thereof is the first source-drain layer or the anode layer;
the first direction is a row direction, and the second direction is a column direction; and
the array substrate further comprises:
data lines arranged on the second source-drain layer, extending along the column direction and arranged at intervals along the row direction, and configured to provide data signals to each of the sub-pixels; and
power supply lines arranged on the second source-drain layer, extending along the column direction and arranged at intervals along the row direction, and configured to provide power supply signals to each of the sub-pixels.

3. The array substrate according to claim 2 , wherein the first conductive layer and the second conductive layer are both the first source-drain layers, the initialization signal lines extend along the row direction, and the connection lines extend along the column direction, each of the initialization signal lines is connected to each of the connection lines and intersected in a grid shape.

4. The array substrate according to claim 3 , wherein:
the array substrate further comprises a first gate line layer and a second gate line layer disposed on the base substrate;
the sub-pixel further comprises a sub-pixel driving circuit, the sub-pixel driving circuit comprising a capacitor and a driving transistor, the capacitor comprising a first plate and a second plate, the first plate being arranged in the first gate line layer, the second plate being arranged in the second gate line layer, the first plate of the capacitor being multiplexed as a gate of the driving transistor, and a first electrode of the driving transistor being connected to the power supply line;
the first source-drain layer is further provided with a plurality of third conductive connection parts, and the third conductive connection parts are distributed in each sub-pixel region; and
the third conductive connection part is connected to the first electrode of the driving transistor through a via hole, and the third conductive connection part is further connected to the power supply line through a via hole, such that the power supply line is electrically connected to the first electrode of the driving transistor through the third conductive connection part.

5. The array substrate according to claim 4 , wherein:
the array substrate further comprises a plurality of scan lines, the scan lines are provided in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are configured to provide scanning signals to each of the sub-pixels;
the sub-pixel driving circuit further comprises a first transistor, a gate of the first transistor is connected to the scan line, a first electrode of the first transistor is connected to the data line, and a second electrode of the first transistor is connected to the second plate of the capacitor;
the first source-drain layer is further provided with a plurality of fourth conductive connection parts, and the fourth conductive connection parts are distributed in each sub-pixel region; and
the fourth conductive connection part is connected to the first electrode of the first transistor through a via hole, and the fourth conductive connection part is further connected to the data line through a via hole, such that the data line is electrically connected to the first electrode of the first transistor through the fourth conductive connection part.

6. The array substrate according to claim 5 , wherein:
the sub-pixel comprises an anode disposed in the anode layer; the array substrate further comprises a plurality of reset signal lines, the reset signal lines are disposed in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are configured to provide reset signals to each of the sub-pixels;
the sub-pixel driving circuit further comprises an eighth transistor, a gate of the eighth transistor is connected to the reset signal line, a first electrode of the eighth transistor is electrically connected to the initialization signal line, and a second electrode of the eighth transistor is electrically connected to the anode of the sub-pixel;
the first source-drain layer is further provided with a plurality of fifth conductive connection parts, the second source-drain layer is further provided with a plurality of sixth conductive connection parts, and the fifth conductive connection parts and the sixth conductive connection parts are distributed in each sub-pixel region; and
the fifth conductive connection part and the second electrode of the eighth transistor are connected through a via hole, the fifth conductive connection part and the sixth conductive connection part are connected through a via hole, and the sixth conductive connection part and the anode are connected through a via hole, such that the second electrode of the eighth transistor is electrically connected to the anode of the sub-pixel.

7. The array substrate according to claim 6 , wherein:
the array substrate further comprises a plurality of light-emitting control signal lines, the light-emitting control signal lines are disposed in the first gate line layer, extend along the row direction and are arranged at intervals along the column direction, and are configured to provide light-emitting control signals to each of the sub-pixels;
the sub-pixel driving circuit further comprises a second transistor and a ninth transistor, a gate of the second transistor is connected to the scan line, and a first electrode of the second transistor is connected to a second electrode of the driving transistor, a second electrode of the second transistor is connected to the first plate of the capacitor; a gate of the ninth transistor is connected to the light-emitting control signal line, and a first electrode of the ninth transistor is electrically connected to the first plate of the capacitor;
the first source-drain layer is further provided with a plurality of first conductive connection parts, and the first conductive connection parts are distributed in each sub-pixel region; and
the first conductive connection part is connected to the second electrode of the second transistor and the first electrode of the ninth transistor through a via hole, and the

Assignees

• Boe Technology Group Co Ltd

Inventors

• Han Long
• Liu Libin
• Huangfu Lujiang

Classifications

• H10K59/8051

  Anodes · CPC title

• H10K77/00

  Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80 · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title