Metal gate structures for field effect transistors

Patent metadata

Field	Value
Publication number	US-12336265-B2
Application number	US-202318151575-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	Sep 27, 2018
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

The present disclosure describes a method for the formation of gate stacks having two or more titanium-aluminum (TiAl) layers with different Al concentrations (e.g., different Al/Ti ratios). For example, a gate structure can include a first TiAl layer with a first Al/Ti ratio and a second TiAl layer with a second Al/Ti ratio greater than the first Al/Ti ratio of the first TiAl layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate;
a dielectric stack surrounding a portion of the fin structure;
a stack of metal-based layers disposed on the dielectric stack;
a first titanium-aluminum (TiAl) layer comprising a first Al/Ti ratio disposed on the stack of metal-based layers; and
a second TiAl layer, disposed on the first TiAl layer, comprising a second Al/Ti ratio greater than the first Al/Ti ratio.

2. The semiconductor device of claim 1 , wherein the dielectric stack comprises a high-k dielectric layer.

3. The semiconductor device of claim 1 , wherein the stack of metal-based layers comprises a metal nitride layer disposed directly on the dielectric stack.

4. The semiconductor device of claim 1 , wherein the stack of metal-based layers comprises:
a first metal nitride layer disposed directly on the dielectric stack; and
a second metal nitride layer disposed directly on the first metal nitride layer, wherein a metal of the first metal nitride layer is different from a metal of the second metal nitride layer.

5. The semiconductor device of claim 1 , further comprising a titanium nitride layer disposed on the second TiAl layer.

6. The semiconductor device of claim 1 , wherein the first Al/Ti ratio is equal to or less than about 80% of the second Al/Ti ratio.

7. The semiconductor device of claim 1 , further comprising a third TiAl layer, disposed on the second TiAl layer, comprising a third Al/Ti ratio less than the second Al/Ti ratio.

8. The semiconductor device of claim 1 , further comprising a third TiAl layer, disposed on the second TiAl layer, comprising a third Al/Ti ratio substantially equal to the first Al/Ti ratio.

9. The semiconductor device of claim 1 , wherein the first TiAl is disposed directly on a tantalum nitride layer of the stack of metal-based layers.

10. The semiconductor device of claim 1 , wherein the first TiAl is disposed directly on a titanium nitride layer or a tungsten nitride layer of the stack of metal-based layers.

11. A semiconductor device, comprising:
a substrate;
a fin structure disposed on the substrate; and
a gate structure, disposed on the fin structure, comprising:
a first titanium-aluminum (TiAl) layer comprising a first Al/Ti ratio;
a second TiAl layer, disposed on the first TiAl layer, comprising a second Al/Ti ratio greater than the first Al/Ti ratio; and
a third TiAl layer, disposed on the second TiAl layer, comprising a third Al/Ti ratio less than the second Al/Ti ratio.

12. The semiconductor device of claim 11 , wherein the third Al/Ti ratio is substantially equal to the first Al/Ti ratio.

13. The semiconductor device of claim 11 , wherein the first Al/Ti ratio is equal to or less than about 80% of the second Al/Ti ratio.

14. The semiconductor device of claim 11 , wherein each of the first and second TiAl layers has a thickness between about 30% and about 300% of that of the third TiAl layer.

15. The semiconductor device of claim 11 , wherein the gate structure further comprises a stack of metal-based layers disposed between the third TiAl layer and the fin structure.

16. The semiconductor device of claim 11 , wherein the gate structure further comprises a metal nitride layer disposed between the third TiAl layer and the fin structure.

17. A method, comprising:
forming a fin structure on a substrate;
depositing a dielectric layer on the fin structure;
depositing a stack of metal-based layers on the dielectric layer;
depositing, on the stack of metal-based layers, a first titanium-aluminum (TiAl) layer comprising a first Al/Ti ratio with a non-zero value; and
depositing, on the first TiAl layer, a second TiAl layer comprising a second Al/Ti ratio greater than the first Al/Ti ratio.

18. The method of claim 17 , wherein depositing the stack of metal-based layers comprises:
depositing a titanium nitride layer directly on the dielectric layer; and
depositing a tantalum nitride layer directly on the titanium nitride layer.

19. The method of claim 17 , wherein depositing the first TiAl layer comprises depositing the first TiAl layer with a varying Al/Ti ratio between a top surface and a bottom surface of the first TiAl layer.

20. The method of claim 17 , further comprising depositing, on the second TiAl layer, a third TiAl layer comprising a third Al/Ti ratio less than the second Al/Ti ratio.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chih-Wei
• Tsai Chia-Ming
• Liu Ke-Chih
• Savant Chandrashekhar Prakash
• Yu Tien-Wei

Classifications

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0135

  Manufacturing their gate conductors · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title