Signal processing device and control method for signal processing device

US12334947B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12334947-B2
Application numberUS-202118040809-A
CountryUS
Kind codeB2
Filing dateJun 29, 2021
Priority dateNov 9, 2020
Publication dateJun 17, 2025
Grant dateJun 17, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-and-hold circuit into a digital signal, and a predetermined voltage is applied to the second capacitor, thereby charging the second capacitor, and the sample-and-hold circuit is then caused to sample the analog signal that has passed through the filter circuit. This suppresses the time required to charge the first capacitor and reduces errors in digital signals.

First claim

Opening claim text (preview).

The invention claimed is: 1. A signal processing device comprising: a filter circuit including a first capacitor for reducing a predetermined frequency component of a sinusoidal analog signal; a sample-and-hold circuit including a second capacitor for sampling and holding the sinusoidal analog signal that has passed through the filter circuit; an AD conversion circuit for converting an output signal from the sample-and-hold circuit into a digital signal; a voltage application circuit for applying a predetermined voltage to the second capacitor; and a control unit for applying the predetermined voltage to the second capacitor through the voltage application circuit, thereby charging the second capacitor, and then causing the sample-and-hold circuit to sample the sinusoidal analog signal that has passed through the filter circuit, wherein the predetermined voltage is ½ of the reference voltage of the AD conversion circuit. 2. The signal processing device according to claim 1 , wherein the sinusoidal analog signal is a sine wave signal or a cosine wave signal output from a rotation angle sensor that detects the rotor angle of a motor. 3. A signal processing device comprising: a filter circuit including a first capacitor for reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor for sampling and holding the analog signal that has passed through the filter circuit; an AD conversion circuit for converting an output signal from the sample-and-hold circuit into a digital signal; a voltage application circuit for applying a predetermined voltage to the second capacitor; and a control unit for applying the predetermined voltage to the second capacitor through the voltage application circuit, thereby charging the second capacitor, and then causing the sample-and-hold circuit to sample the analog signal that has passed through the filter circuit, wherein the sample-and-hold circuit includes a first switch for switching between a sample mode and a hold mode, and the voltage application circuit includes a second switch connected in parallel with the first switch, the second switch controlling electrical connection between a power supply whose output voltage is the predetermined voltage, and the second capacitor, and the signal processing device further comprising a third switch on a line that connects the ground and a point between the first switch and the sample-and-hold circuit. 4. A signal processing device comprising: a filter circuit including a first capacitor for reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor for sampling and holding the analog signal that has passed through the filter circuit; an AD conversion circuit for converting an output signal from the sample-and-hold circuit into a digital signal; a voltage application circuit for applying a predetermined voltage to the second capacitor; and a control unit for applying the predetermined voltage to the second capacitor through the voltage application circuit, thereby charging the second capacitor, and then causing the sample-and-hold circuit to sample the analog signal that has passed through the filter circuit, wherein the sample-and-hold circuit includes a first switch for switching between a sample mode and a hold mode, the voltage application circuit includes a second switch connected in parallel with the first switch, the second switch controlling electrical connection between a power supply whose output voltage is the predetermined voltage, and the second capacitor, the control unit switches the second switch to on from off to charge the second capacitor equivalent to the predetermined voltage, switches the second switch to off from on to cause a signal equivalent to the predetermined voltage to be output from the sample-and-hold circuit, switches the first switch to on from off to charge the second capacitor equivalent to the voltage of the analog signal, and switches the first switch to off from on to cause a signal equivalent to the voltage of the analog signal to be output from the sample-and-hold circuit.

Assignees

Inventors

Classifications

  • with intermediate conversion to phase of sinusoidal {or similar periodical} signals · CPC title

  • by filtering · CPC title

  • H03M1/1255Primary

    Synchronisation of the sampling frequency or phase to the input frequency or phase · CPC title

  • H02P6/16Primary

    Circuit arrangements for detecting position · CPC title

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Frequently asked questions

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What does patent US12334947B2 cover?
A signal processing device and a control method therefor comprise: a filter circuit including a first capacitor and reducing a predetermined frequency component of an analog signal; a sample-and-hold circuit including a second capacitor and sampling and holding the analog signal that has passed through the filter circuit; and an AD conversion circuit converting an output signal from the sample-…
Who is the assignee on this patent?
Hitachi Astemo Ltd
What technology area does this patent fall under?
Primary CPC classification H03M1/1255. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 17 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 6 related publications on this page (citations in our corpus or others sharing the same primary CPC).