Multi-point reference distribution circuit

Patent metadata

Field	Value
Publication number	US-12334944-B2
Application number	US-202318394031-A
Country	US
Kind code	B2
Filing date	Dec 22, 2023
Priority date	Jun 27, 2023
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A circuit includes an amplifier, a pre-driver circuit, and an output circuit. The amplifier has a first input, a second input, and an output. The pre-driver circuit has an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier. The output circuit includes a first transistor and a second transistor. The first transistor has a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit. The second transistor has a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.

First claim

What is claimed is:

1. A circuit comprising:
an amplifier having first and second inputs and an output;
a first transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal;
a second transistor having a first terminal, a second terminal coupled to the first terminal of the first transistor, and a control terminal;
a third transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and a control terminal coupled to the second terminal of the second transistor;
a fourth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal;
a fifth transistor having a control terminal, a first terminal coupled to the second terminal of the fourth transistor, and a second terminal coupled to a reference terminal; and
a sixth transistor having a control terminal coupled to the first terminal of the fifth transistor, a first terminal coupled to the second terminal of the third transistor, and a second terminal coupled to the reference terminal.

2. The circuit of claim 1 , further comprising:
a seventh transistor having a control terminal coupled to the first terminal of the first transistor, a first terminal, and a second terminal coupled to the second terminal of the third transistor.

3. The circuit of claim 2 , further comprising:
an eighth transistor having a first terminal coupled to the first terminal of the third transistor, a second terminal coupled to the control terminal of the seventh transistor, and a control terminal coupled to the control terminal of the second transistor; and
a ninth transistor having a first terminal coupled to the second terminal of the eighth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output of the amplifier.

4. The circuit of claim 2 , further comprising:
an eighth transistor having a control terminal coupled to the first terminal of the sixth transistor, a first terminal coupled to the second terminal of the seventh transistor, and a second terminal coupled to the reference terminal.

5. The circuit of claim 4 , further comprising:
a ninth transistor having a first terminal coupled to the first terminal of the third transistor, a second terminal coupled to the control terminal of the eighth transistor, and a control terminal coupled to the output of the amplifier; and
a tenth transistor having a first terminal coupled to the second terminal of the ninth transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the control terminal of the fifth transistor.

6. The circuit of claim 4 , further comprising:
a first resistor and a first capacitor coupled in series between the control terminal of the seventh transistor and a reference terminal; and
a second resistor and a second capacitor coupled in series between the control terminal of the eighth transistor and the reference terminal.

7. The circuit of claim 1 , further comprising:
a first resistor and a first capacitor coupled in series between the control terminal of the third transistor and a reference terminal; and
a second resistor and a second capacitor coupled in series between the control terminal of the sixth transistor and the reference terminal.

8. A circuit comprising:
an amplifier having a first input, a second input, and an output;
a pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier; and
an output circuit including:
a first transistor having a control terminal coupled to the first output of the pre-driver circuit; a first terminal, and a second terminal coupled to the third output of the pre-driver circuit; and
a second transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to the second terminal of the first transistor, and a second terminal coupled to a reference terminal.

9. The circuit of claim 8 , wherein the pre-driver circuit includes:
a third transistor having a control terminal coupled to the output of the amplifier, a first terminal configured as the first output of the pre-driver circuit, and a second terminal coupled to a reference terminal;
a fourth transistor having a first terminal, and a second terminal coupled to the first terminal of the third transistor, and a control terminal; and
a fifth transistor having a first terminal, a second terminal coupled to the second input of the amplifier, and configured as the third output of the pre-driver circuit, and a control terminal coupled to the second terminal of the fourth transistor;
a sixth transistor having a control terminal coupled to the output of the amplifier, a first terminal, and a second terminal configured as the second output of the pre-driver circuit;
a seventh transistor having a control terminal, a first terminal coupled to the second terminal of the sixth transistor, a second terminal coupled to the reference terminal; and
an eighth transistor having a control terminal coupled to the first terminal of the seventh transistor, a first terminal coupled to the second terminal of the fifth transistor, and a second terminal coupled to the reference terminal.

10. The circuit of claim 9 , wherein the pre-driver circuit includes:
a first snubber circuit coupled to the control terminal of the fifth transistor; and
a second snubber circuit coupled to the control terminal of the eighth transistor.

11. The circuit of claim 8 , wherein the output circuit includes:
a third transistor having a first terminal, a second terminal coupled to the control terminal of the first transistor, and a control terminal coupled to a first bias voltage circuit; and
a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to the output of the amplifier.

12. The circuit of claim 8 , wherein the output circuit includes:
a third transistor having a first terminal, a second terminal coupled to the control terminal of the second transistor, and a control terminal coupled to the output of the amplifier; and
a fourth transistor having a first terminal coupled to the second terminal of the third transistor, a second terminal coupled to the reference terminal, and a control terminal coupled to a second bias voltage circuit.

13. The circuit of claim 8 , further comprising:
a first snubber circuit coupled to the control terminal of the first transistor; and
a second snubber circuit coupled to the control terminal of the second transistor.

14. An analog-to-digital converter (ADC) comprising:
a first capacitive digital-to-analog converter (CDAC) having an input;
a second CDAC having an input;
a reference buffer coupled to the first CDAC and the second CDAC, the reference buffer including:
an amplifier having a first input, a second input, and an output;
a pre-driver circuit having an input coupled to the output of the amplifier, a first output, a second output, and a third output coupled to the second input of the amplifier; and
an output circuit including:
a first transistor having a control terminal coupled to the first output of the pre-driver circuit, a first terminal, and a second terminal coupled to the third output of the pre-driver circuit and the input of the first CDAC;
a second transistor having a control terminal coupled to the second output of the pre-driver circuit, a first terminal coupled to

Assignees

• Texas Instruments Inc

Inventors

• Ghosh Sovan
• Pentakota Visvesvaraya Appala

Classifications

• G05F1/46

  wherein the variable actually regulated by the final control device is DC (G05F1/625 takes precedence) · CPC title

• G06F3/041

  Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means · CPC title

• H03M1/08

  of noise {(H03M1/0617 takes precedence)} · CPC title

• H03M1/06 Primary

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title