Power amplifier output matching

US12334883B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12334883-B2
Application numberUS-202318377464-A
CountryUS
Kind codeB2
Filing dateOct 6, 2023
Priority dateJan 3, 2020
Publication dateJun 17, 2025
Grant dateJun 17, 2025

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to resonate at about three times the fundamental frequency.

First claim

Opening claim text (preview).

What is claimed is: 1. A power amplifier system comprising: a semiconductor-on-insulator die; a power amplifier implemented on the semiconductor-on-insulator die and configured to amplify a radio frequency input signal having a fundamental frequency, the power amplifier; and an output matching circuit including a first second-order harmonic rejection short circuit coupled between an output of the power amplifier and ground, a third-order harmonic rejection open circuit coupled between the output of the power amplifier and a first node, a second-order harmonic rejection open circuit coupled between the output of the power amplifier and the first node, and a second second-order harmonic rejection short circuit positioned between the first node and ground. 2. The power amplifier system of claim 1 wherein the third-order harmonic rejection open circuit is positioned between the output of the power amplifier and a second node, and the second-order harmonic rejection open circuit is positioned between the first node and the second node. 3. The power amplifier system of claim 2 wherein the first and second second-order harmonic rejection short circuits and the second-order harmonic rejection open circuit are configured to resonate at about two times a fundamental frequency of the radio frequency input signal and the third-order harmonic rejection open circuit is configured to resonate at about three times the fundamental frequency. 4. The power amplifier system of claim 1 further comprising biasing circuitry implemented on the semiconductor-on-insulator die and configured to bias the power amplifier, and a switch implemented on the semiconductor-on-insulator die and configured to control connection of signal paths to an antenna. 5. The power amplifier system of claim 1 wherein the power amplifier includes two field effect transistors arranged in a cascode configuration. 6. The power amplifier system of claim 1 wherein the third-order harmonic rejection open circuit includes a capacitor and an inductor, and the inductor is implemented as a surface mount device on a module supporting the semiconductor-on-insulator die. 7. The power amplifier system of claim 6 wherein the first second-order harmonic rejection short circuit includes a tunable bank of at least two capacitors. 8. The power amplifier system of claim 7 further comprising a biasing circuit including a decoupling capacitor and a choke inductor, the choke inductor embedded in a substrate of a module supporting the semiconductor-on-insulator die. 9. A semiconductor-on-insulator die comprising: a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency, the power amplifier; and an output matching circuit including a first second-order harmonic rejection short circuit coupled between an output of the power amplifier and ground, a third-order harmonic rejection open circuit coupled between the output of the power amplifier and a first node, a second-order harmonic rejection open circuit coupled between the output of the power amplifier and the first node, and a second second-order harmonic rejection short circuit positioned between the first node and ground. 10. The semiconductor-on-insulator die of claim 9 wherein the third-order harmonic rejection open circuit is positioned between the output of the power amplifier and a second node, and the second-order harmonic rejection open circuit is positioned between the first node and the second node. 11. The semiconductor-on-insulator die of claim 10 wherein the first and second second-order harmonic rejection short circuits and the second-order harmonic rejection open circuit are configured to resonate at about two times a fundamental frequency of the radio frequency input signal and the third-order harmonic rejection open circuit is configured to resonate at about three times the fundamental frequency. 12. The semiconductor-on-insulator die of claim 9 wherein the power amplifier includes two field effect transistors arranged in a cascode configuration. 13. The semiconductor-on-insulator die of claim 9 wherein the semiconductor-on-insulator die further includes biasing circuitry configured to bias the power amplifier, a switch configured to control connection of signal paths to an antenna, and a controller configured to control the power amplifier and the switch. 14. A mobile device comprising: a module including a semiconductor-on-insulator die mounted thereon, the semiconductor-on-insulator die including a power amplifier implemented on the semiconductor-on-insulator die and configured to amplify a radio frequency input signal having a fundamental frequency, the power amplifier, and an output matching circuit including a first second-order harmonic rejection short circuit coupled between an output of the power amplifier and ground, a third-order harmonic rejection open circuit coupled between the output of the power amplifier and a first node, a second-order harmonic rejection open circuit coupled between the output of the power amplifier and the first node, and a second second-order harmonic rejection short circuit positioned between the first node and ground; and a radio frequency antenna. 15. The mobile device of claim 14 wherein the third-order harmonic rejection open circuit is positioned between the output of the power amplifier and a second node, and the second-order harmonic rejection open circuit is positioned between the first node and the second node. 16. The mobile device of claim 15 wherein the first and second second-order harmonic rejection short circuits and the second-order harmonic rejection open circuit are configured to resonate at about two times a fundamental frequency of the radio frequency input signal and the third-order harmonic rejection open circuit is configured to resonate at about three times the fundamental frequency. 17. The mobile device of claim 14 wherein the radio frequency antenna is included on the module. 18. The mobile device of claim 14 further comprising a biasing circuit including a decoupling capacitor and a choke inductor, the decoupling capacitor implemented on the semiconductor-on-insulator die and the choke inductor embedded in a substrate of the module. 19. The mobile device of claim 14 further wherein the third-order harmonic rejection open circuit includes a capacitor implemented on the semiconductor-on-insulator die and a surface mounted inductor mounted on the module.

Assignees

Inventors

Classifications

  • Portable transceivers · CPC title

  • A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier · CPC title

  • Circuits · CPC title

  • the amplifier being a radio frequency amplifier · CPC title

  • H03F1/565Primary

    using inductive elements · CPC title

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What does patent US12334883B2 cover?
A semiconductor-on-insulator die can include a power amplifier configured to amplify a radio frequency input signal having a fundamental frequency. The die can further include an output matching circuit including first and second second-order harmonic rejection circuits configured to resonate at about two times the fundamental frequency and a third order harmonic rejection circuit configured to…
Who is the assignee on this patent?
Skyworks Solutions Inc
What technology area does this patent fall under?
Primary CPC classification H03F1/565. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jun 17 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).