DC-DC buck converter and operating method thereof

Patent metadata

Field	Value
Publication number	US-12334823-B2
Application number	US-202217828829-A
Country	US
Kind code	B2
Filing date	May 31, 2022
Priority date	Jun 1, 2021
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A DC-DC buck converter for generating an output voltage by stepping down an input voltage includes a converting circuit including a plurality of transistors, a first capacitor, a second capacitor, and an inductor, the converting circuit being configured to form a current path that varies according to a plurality of modes and a plurality of phases; and a control circuit configured to: determine a mode of the converting circuit, from among the plurality of modes, according to a first amplitude of the input voltage and a second amplitude of the output voltage, and determine an ON/OFF state of each transistor of the plurality of transistors according to the determined mode and a phase from among the plurality of phases.

First claim

What is claimed is:

1. A DC-DC buck converter for generating an output voltage by stepping down an input voltage, the DC-DC buck converter comprising:
a converting circuit including a plurality of transistors, a first capacitor, a second capacitor, and an inductor, the converting circuit being configured to form a current path that varies according to a plurality of modes and a plurality of phases; and
a control circuit configured to:
determine a mode of the converting circuit, from among the plurality of modes, according to a first amplitude of the input voltage and a second amplitude of the output voltage, and
determine an ON/OFF state of each transistor of the plurality of transistors according to the determined mode and a phase from among the plurality of phases.

2. The DC-DC buck converter of claim 1 , wherein the plurality of modes comprises a first mode and a second mode, the plurality of phases comprises a first phase, a second phase, and a third phase, and
wherein the converting circuit is further configured to:
operate, while in the first mode, in any one of the first phase or the second phase,
operate, while in the second mode, in any one of the first phase, the second phase, or the third phase, and
output an output current using the first capacitor, the second capacitor, and the inductor in each of the first phase, the second phase, and the third phase.

3. The DC-DC buck converter of claim 2 , wherein the converting circuit is further configured to form the current path via the first capacitor connected to a ground node, the inductor connected to the first capacitor in series, and the second capacitor connected to an input source voltage according to an ON/OFF operation of each of the plurality of transistors in the first phase,
form the current path via the second capacitor connected to the ground node, the first capacitor connected to the second capacitor in series, and the inductor connected to the ground node according to the ON/OFF operation of each of the plurality of transistors in the second phase, and
form the current path via the first capacitor and the inductor connected in parallel and the second capacitor connected to the ground node according to the ON/OFF operation of the plurality of transistors in the third phase.

4. The DC-DC buck converter of claim 2 , wherein in the first phase, a voltage value of a switching node connected to the inductor is a first value obtained by subtracting double the output voltage from the input voltage,
in the second phase, the voltage value of the switching node is 0 V, and
in the third phase, the voltage value of the switching node is a second value obtained by subtracting the output voltage from the input voltage.

5. The DC-DC buck converter of claim 2 , wherein the converting circuit is further configured to, in the second mode, operate in the third phase after operating in the first phase, operate in the second phase after operating in the third phase, and operate in the first phase after operating in the second phase.

6. The DC-DC buck converter of claim 2 , wherein the control circuit is further configured to determine, based on the input voltage and the output voltage, a first time duration in which the first phase is maintained, a second time duration in which the second phase is maintained, and a third time duration in which the third phase is maintained.

7. The DC-DC buck converter of claim 2 , wherein the control circuit comprises:
a first comparator;
a second comparator; and
a compensator including an error amplifier, and
wherein the first comparator is configured to receive a reference signal and an output signal from the error amplifier, and
wherein the second comparator is configured to receive an inverted reference signal having a vertically inverted waveform based on a waveform of the reference signal and the output signal from the error amplifier.

8. The DC-DC buck converter of claim 7 , wherein the reference signal is a sawtooth-shaped signal,
wherein the inverted reference signal is an inverted sawtooth-shaped signal having the vertically inverted waveform based on the waveform of the sawtooth-shaped signal, and
wherein the control circuit is further configured to determine whether the converting circuit is to operate in the first mode or the second mode based on the sawtooth-shaped signal, the inverted sawtooth-shaped signal, and the output signal from the error amplifier.

9. The DC-DC buck converter of claim 8 , wherein the control circuit is further configured to determine the mode is the first mode or the second mode based on a ratio of sections delineated by points in time at which a first magnitude of the sawtooth-shaped signal and a second magnitude of the output signal from the error amplifier are equal and points in time at which a third magnitude of the inverted sawtooth-shaped signal and the second magnitude of the output signal from the error amplifier are equal within one cycle of the sawtooth-shaped signal.

10. The DC-DC buck converter of claim 9 , wherein the control circuit is further configured such that the second magnitude of the output signal from the error amplifier increases as a conversion ratio of the output voltage with respect to the input voltage increases, and a proportion of a time duration in which the third phase is maintained increases in response thereto.

11. The DC-DC buck converter of claim 7 , wherein the control circuit is further configured to switch from the first mode to the second mode when a duty cycle of the converting circuit is determined to be equal to or greater than a threshold.

12. A DC-DC buck converter comprising:
a first transistor connected between an input power source and a first node;
a second transistor connected between the first node and a second node;
a third transistor connected between the second node and a switching node;
a fourth transistor connected between the switching node and a ground node;
a fifth transistor connected between a third node and the ground node;
a sixth transistor connected between the third node and a fourth node;
a seventh transistor connected between the fourth node and a fifth node;
an eighth transistor connected between the fifth node and the ground node;
a first capacitor connected between the second node and the fifth node;
a second capacitor connected between the first node and the third node; and
an inductor connected between the switching node and an output node.

13. The DC-DC buck converter of claim 12 , wherein the DC-DC buck converter is configured to operate in any one of a plurality of phases,
wherein in a first phase of the plurality of phases, the first transistor, the third transistor, the sixth transistor, and the eighth transistor are configured to be turned on, and the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are configured to be turned off, and
wherein in a second phase of the plurality of phases, the second transistor, the fourth transistor, the fifth transistor, and the seventh transistor are configured to be turned on, and the first transistor, the third transistor, the sixth transistor, and the eighth transistor are configured to be turned off.

14. The DC-DC buck converter of claim 13 , wherein in a third phase of the plurality of phases, the second transistor, the third transistor, the fifth transistor, and the seventh transistor are configured to be turned on, and the first transistor, the fourth transistor, the sixth transistor, and the eighth transistor are configured to be turned off.

15. The DC-DC buck converter of claim 12 , further

Assignees

• Samsung Electronics Co Ltd
• Univ Korea Res & Bus Found

Inventors

• Yoo Sungmin
• Lee Hyungmin
• Jung Woojoong
• Kong Taehwang
• Yang Junhyeok
• Lee Yunho

Classifications

• H02M3/158 Primary

  including plural semiconductor devices as final control devices for a single load · CPC title

• H02M3/07

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/156 Primary

  with automatic control of output voltage or current, e.g. switching regulators · CPC title

• H02M1/0095 Primary

  Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck · CPC title