Multi-height interconnect trenches for resistance and capacitance optimization

Patent metadata

Field	Value
Publication number	US-12334392-B2
Application number	US-201916534063-A
Country	US
Kind code	B2
Filing date	Aug 7, 2019
Priority date	Aug 7, 2019
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.

First claim

What is claimed is:

1. An interconnect layer, comprising:
an interlayer dielectric (ILD);
a first interconnect disposed in the ILD along a first track, wherein the first interconnect has a first height;
a second interconnect disposed in the ILD along a second track, wherein the second interconnect has a second height that is less than the first height;
a third interconnect disposed in the ILD along a third track, wherein the third interconnect has a third height that is between the first height and the second height, wherein the second interconnect is laterally between the third interconnect and the first interconnect;
a fourth interconnect disposed in the ILD along a fourth track, wherein the fourth interconnect has the first height, wherein the fourth interconnect is laterally between the second interconnect and the third interconnect;
a fifth interconnect disposed in the ILD along a fifth track, wherein the fifth track has the second height, wherein the fifth interconnect is adjacent to a side of the third interconnect opposite the fourth interconnect, and wherein each of the first interconnect, the second interconnect, the third interconnect, the fourth interconnect, and the fifth interconnect has a bottommost surface above a bottommost surface of the ILD; and
a via through the ILD, the via laterally between the third interconnect and the fourth interconnect.

2. The interconnect layer of claim 1 , wherein the first interconnect is separated from the second interconnect by a dielectric material.

3. The interconnect layer of claim 1 , wherein a ratio of the first height to the second height is approximately 4:1 or smaller.

4. The interconnect layer of claim 1 , wherein a width of the first interconnect is substantially equal to a width of the second interconnect.

5. The interconnect layer of claim 1 , wherein a first surface of the first interconnect is substantially coplanar with a first surface of the second interconnect.

6. The interconnect layer of claim 1 , further comprising:
a first etchstop layer in the ILD, wherein the first etchstop layer is below the first interconnect; and
a second etchstop layer in the ILD, wherein the second etchstop layer is below the second interconnect.

7. The interconnect layer of claim 1 , wherein the ILD further comprises:
a first ILD;
a second ILD; and
a third ILD, wherein the first ILD, the second ILD, and the third ILD are etch selective to each other.

8. A semiconductor device, comprising:
a semiconductor substrate; and
a plurality of interconnect layers over the semiconductor substrate, wherein one or more of the interconnect layers comprise:
an interlayer dielectric (ILD);
a first interconnect disposed in the ILD along a first track, wherein the first interconnect has a first height;
a second interconnect disposed in the ILD along a second track, wherein the second interconnect has a second height that is less than the first height;
a third interconnect disposed in the ILD along a third track, wherein the third interconnect has a third height that is between the first height and the second height, wherein the second interconnect is laterally between the third interconnect and the first interconnect;

a fourth interconnect disposed in the ILD along a fourth track, wherein the fourth interconnect has the first height, wherein the fourth interconnect is laterally between the second interconnect and the third interconnect;
a fifth interconnect disposed in the ILD along a fifth track, wherein the fifth track has the second height, wherein the fifth interconnect is adjacent to a side of the third interconnect opposite the fourth interconnect, and wherein each of the first interconnect, the second interconnect, the third interconnect, the fourth interconnect, and the fifth interconnect has a bottommost surface above a bottommost surface of the ILD; and
a via through the ILD, the via laterally between the third interconnect and the fourth interconnect.

9. The semiconductor device of claim 8 , wherein a first interconnect layer and a second interconnect layer both comprise the first interconnect and the second interconnect.

10. The semiconductor device of claim 9 , wherein the first interconnect layer is directly below the second interconnect layer.

11. The semiconductor device of claim 8 , wherein the first interconnect layer is spaced apart from the second interconnect layer by one or more intervening interconnect layers.

12. The semiconductor device of claim 8 , wherein at least one of the plurality of interconnect layers comprises interconnects with a uniform height.

13. An electronic system, comprising:
a board; and
an electronic package electrically coupled to the board, wherein the electronic package comprises a semiconductor die, and wherein the die comprises:
an interconnect layer with first interconnects, second interconnects, third interconnect, fourth interconnects, and fifth interconnects in an interlayer dielectric (ILD) along corresponding tracks, wherein a height of the second interconnects is less than a height of the first interconnects, wherein a height of the third interconnects is between the height of the first interconnects and the height of the second interconnects, wherein the fourth interconnects have the height of the first interconnects, wherein the fifth interconnects have the height of the second interconnects, wherein one of the second interconnects is laterally between one of the third interconnects and one of the first interconnects, wherein one of the fourth interconnects is laterally between the one of the second interconnects and the one of the third interconnects, wherein one of the fifth interconnects is adjacent to a side of the one of the third interconnects opposite the one of the fourth interconnects, and wherein each of the first interconnects, the second interconnects, the third interconnects, the fourth interconnects, and the fifth interconnects has a bottommost surface above a bottommost surface of the ILD, and the interconnect layer further comprising a via through the ILD, the via laterally between the one of the third interconnects and the one of the fourth interconnects.

14. The electronic system of claim 13 , wherein the interconnect layer further comprises a first etchstop layer and a second etchstop layer within the ILD.

15. A method of forming an interconnect layer, comprising:
disposing a grating over an interlayer dielectric (ILD);
forming first trenches into the ILD through the grating along a first track, wherein the first trenches have a first depth;
forming second trenches into the ILD along a second track, wherein the second trenches have a second depth that is less than the first depth;
forming third trenches into the ILD along a third track, wherein the third trenches have a third depth that is between the first depth and the second depth;
forming fourth trenches into the ILD along a fourth track, wherein the fourth trenches have the first depth, wherein one of the second trenches is laterally between one of the third trenches and one of the first trenches, wherein one of the fourth trenches is laterally between the one of the second trenches and the one of the third trenches;
forming fifth trenches into the ILD along a fifth track, wherein the fifth trenches have the second depth, wherein one of the fifth trenches is adjacent to a side of the one of the third trenches opposite the one of the fourth trenches, and wherein each of the first trenches, the second trenches, the third trenches, the fourth trenches, and the fifth trenches has a bottommost surface above a bottommost surface of the

Assignees

• Intel Corp

Inventors

• Lin Kevin Lai
• Kobrinsky Mauro
• Anders Mark
• Kaul Himanshu
• Krishnamurthy Ram

Classifications

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/087 Primary

  involving multiple stacked pre-patterned masks · CPC title