Data integrity checks based on voltage distribution metrics

US12334166B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12334166-B2
Application numberUS-202318373741-A
CountryUS
Kind codeB2
Filing dateSep 27, 2023
Priority dateDec 16, 2020
Publication dateJun 17, 2025
Grant dateJun 17, 2025

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

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Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a first threshold criterion, obtaining, from a neural network, a value of a voltage distribution metric associated with the page; and upon determining that the voltage distribution metric value satisfies a second threshold criterion, performing a media management operation with respect to a block associated with the page, wherein the media management operation comprises writing data stored at the block to a new block.

First claim

Opening claim text (preview).

What is claimed is: 1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, to perform operations comprising: determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a threshold criterion, providing, to a neural network, at least two different voltage distribution metrics values currently associated with the memory page, wherein each voltage distribution metrics value reflects one of a voltage distribution margin, a voltage distribution floor, or a voltage distribution center; and obtaining, from the neural network, a recommendation to trigger a media management operation with respect to a block associated with the memory page. 2. The system of claim 1 , wherein the data state metric value comprises a raw bit error rate (RBER) or a bit error count (BER). 3. The system of claim 1 , wherein one or more of the voltage distribution metric values are determined using a vectorized read level calibration (vRLC) procedure. 4. The system of claim 1 , wherein the operations further comprise: obtaining, from the neural network, a recommendation to select a new memory page. 5. The system of claim 1 , wherein the operations further comprise: responsive to the data state metric value failing to satisfy the threshold criterion, determining a new value of the data state metric of another memory page associated with the block. 6. The system of claim 1 , wherein the media management operation comprises writing data stored at the block to a new block. 7. A method, comprising: determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a threshold criterion, providing, to a neural network, at least two different voltage distribution metrics values currently associated with the memory page, wherein each voltage distribution metrics value reflects one of a voltage distribution margin, a voltage distribution floor, or a voltage distribution center; and obtaining, from the neural network, a recommendation to trigger a media management operation with respect to a block associated with the memory page. 8. The method of claim 7 , wherein the data state metric value comprises a raw bit error rate (RBER) or a bit error count (BER). 9. The method of claim 7 , wherein one or more of the voltage distribution metric values are determined using a vectorized read level calibration (vRLC) procedure. 10. The method of claim 7 , wherein: obtaining, from the neural network, a recommendation to select a new memory page. 11. The method of claim 7 , further comprising: responsive to the data state metric value failing to satisfy the threshold criterion, determining a new value of the data state metric of another memory page associated with the block. 12. The method of claim 7 , wherein the media management operation comprises writing data stored at the block to a new block. 13. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device operatively coupled to a memory, performs operations comprising: determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric value satisfies a threshold criterion, providing, to a neural network, at least two different voltage distribution metrics values currently associated with the memory page, wherein each voltage distribution metrics value reflects one of a voltage distribution margin, a voltage distribution floor, or a voltage distribution center; and obtaining, from the neural network, a recommendation to trigger a media management operation with respect to a block associated with the memory page. 14. The non-transitory computer-readable storage medium of claim 13 , wherein the data state metric value comprises a raw bit error rate (RBER) or a bit error count (BER). 15. The non-transitory computer-readable storage medium of claim 13 , wherein one or more of the voltage distribution metric values are determined using a vectorized read level calibration (vRLC) procedure. 16. The non-transitory computer-readable storage medium of claim 13 , wherein the operations further comprise: obtaining, from the neural network, a recommendation to select a new memory page. 17. The non-transitory computer-readable storage medium of claim 13 , wherein the operations further comprise: responsive to the data state metric value failing to satisfy the threshold criterion, determining a new value of the data state metric of another memory page associated with the block.

Assignees

Inventors

Classifications

  • Indication or identification of errors, e.g. for repair · CPC title

  • of threshold voltage · CPC title

  • Calibration · CPC title

  • comprising voltage or current generators · CPC title

  • Sensing or reading circuits; Data output circuits · CPC title

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Frequently asked questions

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What does patent US12334166B2 cover?
Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including determining a value of a data state metric of a memory page, wherein the data state metric value is reflective of a number of bit errors associated with the memory page; upon determining that the data state metric va…
Who is the assignee on this patent?
Micron Technology Inc
What technology area does this patent fall under?
Primary CPC classification G11C16/0483. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Jun 17 2025 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).