Aperture access processors, methods, systems, and instructions

Patent metadata

Field	Value
Publication number	US-12333325-B2
Application number	US-202217898397-A
Country	US
Kind code	B2
Filing date	Aug 29, 2022
Priority date	Jul 1, 2016
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

A processor of an aspect includes a decode unit to decode an aperture access instruction, and an execution unit coupled with the decode unit. The execution unit, in response to the aperture access instruction, is to read a host physical memory address, which is to be associated with an aperture that is to be in system memory, from an access protected structure, and access data within the aperture at a host physical memory address that is not to be obtained through address translation. Other processors are also disclosed, as are methods, systems, and machine-readable medium storing aperture access instructions.

First claim

What is claimed is:

1. A processor comprising: a decode unit to decode a write to memory instruction of software being performed by a virtual machine, the write to memory instruction to indicate a source register and to indicate a first offset, the source register to have data; and an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the write to memory instruction, including to: read a memory address from an access-protected on-die storage location dedicated to storing the memory address, wherein the access-protected on-die storage location is not an address translation structure, the memory address corresponding to a base of an access-protected range in system memory, the access-protected range having a plurality of storage locations, each at a different offset from the base, including a first storage location at the first offset from the base; and store the data to the first storage location of the access-protected range, wherein the storage of the data to the first storage location of the access-protected range is configured to provide the data from the virtual machine to another entity.

2. The processor of claim 1 , wherein the memory address is the base address, and wherein the memory address is a physical memory address.

3. The processor of claim 1 , wherein the access-protected on-die storage location is a virtualization control storage location.

4. The processor of claim 1 , wherein the write to memory instruction has a special privilege to access the access-protected on-die storage location, and wherein a plurality of read from memory instructions and a plurality of write to memory instructions do not have the special privilege to access the access-protected on-die storage location.

5. The processor of claim 1 , wherein access to the access-protected on-die storage location is to be restricted based on a type of instruction used to access it.

6. The processor of claim 1 , wherein the entity is a second virtual machine.

7. The processor of claim 1 , wherein the access-protected range is an aperture between the virtual machine and the entity.

8. The processor of claim 1 , wherein the instruction does not indicate memory address information for the memory address, and wherein the processor has a reduced instruction set computing (RISC) architecture.

9. The process of claim 1 , wherein the virtual machine does not know the memory address, and wherein a second instruction when performed is not able to access the access-protected on-die storage location.

10. A processor comprising: a decode unit to decode an instruction of software executed in a first virtual machine, the instruction to indicate a source register and to indicate a first offset; and an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the instruction, including to: read a memory address from an access-protected on-die storage location, wherein the access-protected on-die storage location does not contain address translations, the memory address corresponding to a base of an access-protected range of system memory, the access-protected range having a plurality of storage locations, each at a different offset from the base, including a first storage location at the first offset from the base; and store data from the source register to the first storage location of the access-protected range, wherein the access-protected range is configured to provide the data from the first virtual machine to a second virtual machine.

11. The processor of claim 10 , wherein the memory address is a physical memory address.

12. The processor of claim 11 , wherein the access-protected on-die storage location is a virtualization control storage location.

13. The processor of claim 12 , wherein the instruction has a special privilege to access the access-protected on-die storage location, and wherein a plurality of read from memory instructions and a plurality of write to memory instructions do not have the special privilege to access the access-protected on-die storage location.

14. The processor of claim 12 , wherein access to the access-protected on-die storage location is to be restricted based on a type of instruction used to access it.

15. The processor of claim 12 , wherein the access-protected range is an aperture between the first virtual machine and the second virtual machine, and wherein the processor has a reduced instruction set computing (RISC) architecture.

16. A method comprising:
decoding a write to memory instruction of software being performed by a virtual machine, the write to memory instruction indicating a source register and indicating a first offset, the source register having data; and
performing operations corresponding to the write to memory instruction, including:
reading a memory address from an access-protected on-die storage location dedicated to storing the memory address, wherein the reading of the memory address from the access-protected on-die storage location is not part of an address translation process, the memory address being a base of an access-protected range in system memory, the access-protected range having a plurality of storage locations, each at a different offset from the base, including a first storage location at the first offset from the base; and
providing the data from the virtual machine to another entity, including storing the data to the first storage location of the access-protected range.

17. The method of claim 16 , wherein reading the memory address comprises reading a physical memory address, and wherein reading the memory address from the access-protected on-die storage location comprises reading the memory address from a virtualization control storage location.

18. A system comprising: a system memory; and a processor coupled with the system memory, the processor comprising: a decode unit to decode a write to memory instruction of software being performed by a virtual machine, the write to memory instruction to indicate a source register and to indicate a first offset, the source register to have data; and an execution unit coupled with the decode unit, the execution unit to perform operations corresponding to the write to memory instruction, including to: read a memory address from an access-protected on-die storage location dedicated to storing the memory address, wherein the access-protected on-die storage location does not contain address translations, the memory address corresponding to a base of an access-protected range in system memory, the access-protected range having a plurality of storage locations, each at a different offset from the base, including a first storage location at the first offset from the base; and store the data to the first storage location of the access-protected range, wherein the storage of the data to the first storage location of the access-protected range is configured to provide the data from the virtual machine to another entity.

19. The system of claim 18 , wherein the system memory comprises dynamic random access memory (DRAM), and wherein the memory address is a physical memory address.

20. The system of claim 19 , further comprising a storage device coupled with the system memory, and wherein the access-protected on-die storage location is a virtualization control storage location.

21. The system of claim 20 , further comprising an audio input/output device coupled with the processor, and wherein the write to memory instruction has a special privilege to access t

Assignees

• Intel Corp

Inventors

• Huntley Barry E
• Tsai Jr-Shian
• Neiger Gilbert
• Sankaran Rajesh M
• Ergin Mesut A
• Sahita Ravi L
• Herdrich Andrew J
• Wang Wei

Classifications

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title

• G06F2009/45591

  Monitoring or debugging support · CPC title

• G06F2009/45583

  Memory management, e.g. access or allocation · CPC title

• G06F12/10

  Address translation · CPC title

• G06F12/109

  for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence) · CPC title