Reducing probe filter accesses for processing in memory requests

Patent metadata

Field	Value
Publication number	US-12332795-B2
Application number	US-202217719225-A
Country	US
Kind code	B2
Filing date	Apr 12, 2022
Priority date	Apr 12, 2022
Publication date	Jun 17, 2025
Grant date	Jun 17, 2025

Abstract

Systems, apparatuses, and methods for reducing probe filter accesses in response to processing-in-memory (PIM) requests are disclosed. A coherent secondary unit receives PIM requests targeting a corresponding PIM device. For each PIM request that is received, the coherent secondary unit performs a lookup of a PIM address table (PAT). If the address of the PIM request matches an address of an existing entry in the PAT, the coherent secondary unit prevents the PIM request from being sent to a probe filter. Otherwise, if there is no match for the address of the PIM request in the entries of the PAT, the coherent secondary unit sends the PIM request to the probe filter, and the coherent secondary unit creates a new PAT entry for the address of the PIM request. Any subsequent PIM requests to the same address will match with the new entry in the PAT.

First claim

What is claimed is:

1. An apparatus comprising:
a probe filter configured to enforce cache coherency for a given memory range;
a processing-in-memory (PIM) address table (PAT) comprising a plurality of entries with each entry being configured to store:
an address of a PIM request for which probes have been issued; and
a bank mask that indicates which banks of a plurality of banks of a memory device have been targeted by one or more PIM requests, each comprising a corresponding bank mask field; and

a circuit configured to:
perform a lookup of the PAT, responsive to receiving a first PIM request;
responsive to the lookup of the PAT being a miss:
create a first entry in the PAT for the first PIM request; and
send the first PIM request to the probe filter; and

responsive to the lookup of the PAT being a hit, send the first PIM request to a PIM device and not the probe filter.

2. The apparatus as recited in claim 1 , wherein responsive to receiving the first PIM request, the probe filter is configured to send a plurality of probes to one or more cache subsystems to determine if any cache lines targeted by the first PIM request are cached by the one or more cache subsystems.

3. The apparatus as recited in claim 1 , wherein responsive to a first non-PIM request allocating an entry in the probe filter, the circuit is configured to:
search the PAT for entries corresponding to a first address of the first non-PIM request; and
invalidate an entry in the PAT which corresponds to the first address of the first non-PIM request.

4. The apparatus as recited in claim 1 , wherein the first PIM request indicates a computation to be performed in memory.

5. The apparatus as recited in claim 1 , wherein the circuit is further configured to:
perform the lookup of the PAT by indexing into the PAT using an address of the first PIM request; and
generate an indication that the lookup of the PAT is a miss for a given entry of the plurality of entries, responsive to the address of the first PIM request matching the address of the given entry and one or more bits that indicate banks being targeted of the bank mask field of the first PIM request not having corresponding bits of the bank mask field of the given entry indicating banks have been targeted.

6. The apparatus as recited in claim 1 , wherein the circuit is further configured to disable the PAT, responsive to an indication that a PIM mode is deactivated, wherein the PIM mode indicates PIM requests and non-PIM requests are required to be separated by a synchronization operation.

7. The apparatus as recited in claim 1 , wherein the first entry in the PAT for the first PIM request corresponds to a first set of non-contiguous memory regions.

8. A method comprising:
storing, by circuitry in entries of a processing-in-memory (PIM) address table (PAT):
an address of a processing-in-memory (PIM) request for which probes have been issued; and
a bank mask that indicates which banks of a plurality of banks of a memory device have been targeted by one or more PIM requests, each comprising a corresponding bank mask field;

performing, by a circuit, a lookup of the PAT responsive to receiving a first PIM request;
responsive to the lookup of the PAT being a miss:
creating a first entry in the PAT for the first PIM request; and
sending the first PIM request to a probe filter configured to enforce cache coherency for a given memory range; and

responsive to the lookup of the PAT being a hit, sending the first PIM request to a PIM device and not the probe filter.

9. The method as recited in claim 8 , further comprising the probe filter sending a plurality of probes to one or more cache subsystems to determine if any cache lines targeted by the first PIM request are cached by the one or more cache subsystems, responsive to receiving the first PIM request.

10. The method as recited in claim 8 , wherein responsive to a first non-PIM request allocating an entry in the probe filter, the method further comprising:
searching the PAT for entries corresponding to a first address of the first non-PIM request; and
invalidating an entry in the PAT which corresponds to the first address of the first non-PIM request.

11. The method as recited in claim 8 , wherein the first PIM request indicates a computation to be performed in memory.

12. The method as recited in claim 8 , further comprising generating an indication that the lookup of the PAT is a miss for a given entry of a plurality of entries of the PAT, responsive to the address of the first PIM request matching the address of the given entry and one or more bits that indicate banks being targeted of the bank mask of the first PIM request not having corresponding bits of the bank mask of the given entry indicating banks have been targeted.

13. The method as recited in claim 8 , further comprising disabling the PAT, responsive to an indication that a PIM mode is deactivated, wherein the PIM mode indicates PIM requests and non-PIM requests are required to be separated by a synchronization operation.

14. The method as recited in claim 8 , wherein the first entry in the PAT for the first PIM request corresponds to a first set of non-contiguous memory regions.

15. A system comprising:
a processing-in-memory (PIM) device; and
a circuit configured to:
perform a lookup of PIM address table (PAT) responsive to receiving a first processing-in-memory (PIM) request by indexing into the PAT using an address and a bank mask received with the first PIM request, wherein the PAT comprises a plurality of entries, each of the plurality of entries comprising circuitry configured to store:
an address of a PIM request for which probes have been issued; and
a bank mask that indicates which banks of a plurality of banks of a memory device have been targeted by one or more PIM requests, each comprising a corresponding bank mask field;

responsive to the lookup of the PAT being a miss:
create a first entry in the PAT for the first PIM request; and
send the first PIM request to a probe filter configured to enforce cache coherency for a given memory range; and

responsive to the lookup of the PAT being a hit, send the first PIM request to the PIM device and not the probe filter.

16. The system as recited in claim 15 , wherein responsive to receiving the first PIM request, the circuit is configured to send a plurality of probes to one or more cache subsystems to determine if any cache lines targeted by the first PIM request are cached by the one or more cache subsystems.

17. The system as recited in claim 15 , wherein responsive to a first non-PIM request allocating an entry in the probe filter, the circuit is configured to:
search the PAT for entries corresponding to a first address of the first non-PIM request; and
invalidate an entry in the PAT which corresponds to the first address of the first non-PIM request.

18. The system as recited in claim 15 , wherein the first PIM request indicates a computation to be performed in memory.

19. The system as recited in claim 15 , wherein the circuit is further configured to generate an indication that the lookup of the PAT is a miss for a given entry of the plurality of entries, responsive to the address of the first PIM request matching the address of the given entry and one or more bits that indicate banks being targeted of the bank mask of the first PIM request not having corresponding bits of the bank mask field of the given entry indicating banks have been targeted.

20. The system as recited in c

Assignees

• Advanced Micro Devices Inc

Inventors

• Boyer Michael Warren
• Alsop Johnathan

Classifications

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F12/0888

  using selective caching, e.g. bypass · CPC title

• G06F12/0811

  with multilevel cache hierarchies · CPC title

• G06F12/0828 Primary

  with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions · CPC title